R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 348

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 7 Register Banks
7.5
There are two types of register bank exception (register bank error): register bank overflow and
register bank underflow.
7.5.1
(1) Register Bank Overflow
This exception occurs if, after data has been saved to all of the register banks, an interrupt for
which register bank use is allowed is received by the CPU, and the register bank overflow
exception is not masked by the interrupt controller. In this case the bank number (BN) bits in the
bank number register (IBNR) remain set to the maximum value, N, and no data is saved to the
register bank.
(2) Register Bank Underflow
This exception occurs if the RESBANK instruction is executed when no data has been saved to
the register banks. In this case the values of R0 to R14, GBR, MACH, MACL, and PR do not
change. In addition, the bank number (BN) bits in the bank number register (IBNR) remain set to
0.
7.5.2
If a register bank error is generated, register bank error exception processing begins. When this
happens the CPU performs the following operations.
1. The contents of the status register (SR) are saved to the stack.
2. The value of the program counter (PC) is saved to the stack. The PC value that is saved when a
3. The exception service routine start address is extracted from the exception processing vector
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REJ09B0051-0300
register bank overflow occurs is the starting address of the next instruction after the last
executed instruction. The PC value that is saved when a register bank underflow occurs is the
starting address of the relevant RESBANK instruction.
To prevent multiple interrupts from occurring when a bank overflow occurs, the level of the
interrupt that caused the overflow is written to the interrupt mask bits (I3 to I0) of the status
register (SR).
table corresponding to the register bank error, and the program is run beginning from that
address.
Register Bank Exceptions
Register Bank Error Sources
Register Bank Error Exception Processing