R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 40

IC SUPERH MPU ROMLESS 240QFP

R5S72030W200FP

Manufacturer Part Number
R5S72030W200FP
Description
IC SUPERH MPU ROMLESS 240QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7200r
Datasheets

Specifications of R5S72030W200FP

Core Processor
SH2A-FPU
Core Size
32-Bit
Speed
200MHz
Connectivity
CAN, I²C, SCI, SSI, SSU, USB
Peripherals
DMA, LCD, POR, PWM, WDT
Number Of I /o
82
Program Memory Type
ROMless
Ram Size
80K x 8
Voltage - Supply (vcc/vdd)
1.1 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
240-QFP
For Use With
R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-

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Section 3 Exception Handling
3.5
3.5.1
(1) Bank Overflow
(2) Bank Underflow
3.5.2
Register bank error exception handling is started when a register bank error occurs. CPU
operations are as follows.
1. The start address of the exception service routine corresponding to the register bank error is
2. The status register (SR) is saved on the stack.
3. The program counter (PC) is saved on the stack. The saved PC value is the start address of the
4. Execution jumps to the address fetched from the exception handling vector table and program
Rev. 3.00 Jul 08, 2005 page 24 of 484
REJ09B0051-0300
When a save has already been performed to all register bank areas when acceptance of register
overflow exception has been set by interrupt controller, and an interrupt that uses a register
bank is generated and is accepted by the CPU
When an attempt is made to execute a RESBANK instruction when a save has not been
performed to a register bank
fetched from the exception handling vector table.
instruction following the last instruction executed, in the case of a bank overflow, or the start
address of the executed RESBANK instruction, in the case of an underflow. To prevent
multiple interrupts when a bank overflow occurs, the level of the interrupt that is the source of
the bank overflow is written to the interrupt mask level bits (I3 to I0) in the status register
(SR).
execution commences. The jump is not a delayed branch.
Register Bank Errors
Register Bank Error Sources
Register Bank Error Exception Handling

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