R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 360

IC SUPERH MPU ROMLESS 240QFP

R5S72030W200FP

Manufacturer Part Number
R5S72030W200FP
Description
IC SUPERH MPU ROMLESS 240QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7200r
Datasheets

Specifications of R5S72030W200FP

Core Processor
SH2A-FPU
Core Size
32-Bit
Speed
200MHz
Connectivity
CAN, I²C, SCI, SSI, SSU, USB
Peripherals
DMA, LCD, POR, PWM, WDT
Number Of I /o
82
Program Memory Type
ROMless
Ram Size
80K x 8
Voltage - Supply (vcc/vdd)
1.1 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
240-QFP
For Use With
R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-

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Section 8 Pipeline Operation
(3) When the preceding instruction and succeeding instruction are both shift instructions or rotate
(4) When the preceding instruction and succeeding instruction are both FPU arithmetic operation
(5) When the preceding instruction and succeeding instruction are both FPU load/store
Rev. 3.00 Jul 08, 2005 page 344 of 484
REJ09B0051-0300
STS
STS
Note: The two instructions using the multiplication result read bus conflict with each other.
SHAD R0,R1
SHAD R2,R3
FADD FR0,FR1
FADD FR2,FR3
FNEG FR0
FMOV FR1,FR3
Figure 8.14 Example of Contention between Instructions Using Multiplication Result
instructions (figure 8.15)
instructions (figure 8.16)
With regard to FPU arithmetic operation instructions, complex resource contention occurs with
double-precision instructions or with FDIV or FSQRT instructions. See section 8.6,
Contention Due to FPU, for details.
instructions (figure 8.17)
Figure 8.16 Example of FPU Arithmetic Operation Instruction Contention
MACH,R0
FPUL,R1
Figure 8.17 Example of FPU Load/Store Instruction Contention
Figure 8.15 Example of Shift Instruction Contention
IF
IF
IF
IF
IF
IF
IF
IF
ID
DF
DF
ID
EX
ID
E1
DF
EX
DF
Read Bus
EX
ID
EX
E2
E1
NA
EX
mm
MA
SF
E2
SF
NA
mm
WB
SF
SF
mm
WB

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