R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 437

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

(5) Unconditional Branch Instructions with No Delay (JSR/N @@(disp,TBR))
Instruction Types
Pipeline
Operation
The pipeline ends after five stages: IF, ID, EX, MA, EX. Condition determination is performed in
the ID stage. This is not a delayed branch instruction. The branch destination address is calculated
in the second EX stage. All overrun-fetched instructions up to that point are discarded. The branch
destination instruction fetch is started from the slot following the slot with the second EX of
instruction A.
Instruction Issuance
This instruction uses the branch pipeline.
This instruction uses the memory access pipeline.
Parallel Execution Capability
No particular comments
Instruction A
Next instruction
Instruction after next
Second instruction
after next
Branch destination
instruction
JSR/N
@@(disp,TBR)
↔ ↔ ↔ ↔ ↔ Slots
IF
IF
ID
—
IF
IF
EX
⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ (Fetched but discarded)
⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ (Fetched but discarded)
⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ (Fetched but discarded)
—
MA
—
EX
—
IF
Rev. 3.00 Jul 08, 2005 page 421 of 484
ID
Section 8 Pipeline Operation
EX
⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅
REJ09B0051-0300