R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 57

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

4.3
The instruction format table, table 5.8, refers to the source operand and the destination operand.
The meaning of the operand depends on the instruction code. The symbols are used as follows:
Addressing
Mode
Immediate
addressing
xxxx:
mmmm: Source register
nnnn:
iiii:
dddd:
Instruction Format
Instruction
Format
#imm:8
#imm:8
#imm:8
#imm:3
Instruction code
Destination register
Immediate data
Displacement
Effective Addresses Calculation
The 8-bit immediate data (imm) for the TST, AND,
OR, and XOR instructions are zero-extended.
The 8-bit immediate data (imm) for the MOV, ADD,
and CMP/EQ instructions are sign-extended.
Immediate data (imm) for the TRAPA instruction is
zero-extended and is quadrupled.
3-bit immediate data imm of BAND, BOR, BXOR,
BST, BLD, BSET, or BCLR instruction indicates bit
position.
Rev. 3.00 Jul 08, 2005 page 41 of 484
Section 4 Instruction Features
REJ09B0051-0300
Formula
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