R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 168

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 6 Instruction Descriptions
6.3.34
Format
SHLD Rm, Rn
Description
Shifts the contents of general register Rn logically. General register Rm specifies the shift
direction and number of bits to be shifted.
A left shift is performed when the Rm register value is positive, and a right shift when negative.
In a right shift, 0 is added at the upper end.
The number of bits to be shifted is specified by the lower 5 bits (bits 4 to 0) of register Rm. If the
value is negative (MSB = 1), the Rm register value is expressed as a two's complement.
Therefore, the shift amount in a right shift is the value obtained by adding 1 to the inverse of the
lower 5 bits of register Rm. The shift amount is 0 to 31 in a left shift, and 1 to 32 in a right shift.
Rev. 3.00 Jul 08, 2005 page 152 of 484
REJ09B0051-0300
SHLD
Dynamic Logical Shift
Abstract
When Rm ≥ 0, Rn<<Rm → Rn
When Rm < 0, Rn>>|Rm| → [0 → Rn]
SHift Logical Dynamically
Code
0100nnnnmmmm1101
Shift Instruction
Cycle
1
T Bit
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