R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 8

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Item
7.4.2 Register Bank
Addressing
Figure 7.4 Register
Bank Addressing
8.2 Slots and
Pipeline Flow
Figure 8.3
Impossible Pipeline
Flow (1)
8.6 Contention Due
to FPU
Figure 8.36
Example of Use of
Result of Zero-
Latency Instruction
as Source
8.9 Pipeline
Operations for Each
Instruction
Table 8.1 Number
of Instruction Stages
and Execution States
Appendix A SH-
2A/SH2A-FPU
Parallel Execution
Rev. 3.00 Jul 08, 2005 page vi of xiv
Page
330
331
339
353
372
480,
481
Revision (See Manual for Details)
Description amended
⋅⋅⋅ and the entry within the bank (R0 to R14, GBR, MACH, MACL,
PR, VTO) is specified by address bits 6 to 2 (EN).
Figure amended
(Before) IVO → (After) VTO
Figure amended
Instruction 1
Figure amended
(Before) GX → (After) EX
Table amended
Table amended
MW
EX
BR
System
control
instructions
Instruction
cation of
Classifi-
First
Type
MW
EX
MR
Instruction
cation of
Classifi-
Second
MAC
register
transfer
instructions
Category
STC.L
SUBC
JSR/N
of Stages
Number
IF ID EX MA WB
4
VBR,@-Rn
Rm,Rn
@@(disp8,TBR)
Execution
States
1
Latency
STS.L
SUBV
2
• These instruc-
Instruction
tions use the
multiplication
result read path.
Contention
PR,@-Rn
Rm,Rn
STS
STS
TST
Instructions
MACH,Rn
MACL,Rn
#imm,R0