R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 463

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

(4) FPU Exception Handling
Instruction Type
FPU exception handling
Pipeline
Operation
An FPU execution is accepted in the ID stage of an instruction, and processing from that ID stage
onward is replaced by the FPU exception handling sequence.
The pipeline ends after six stages: IF, ID, EX, MA, MA, MA. FPU exception handling is not a
delayed branch. The IF stage of the branch destination instruction is started from the slot
containing the last MA stage of the FPU exception handling.
Pipeline Processing of Instructions from Generation to Acceptance of FPU Exceptions
The FPU makes the instruction at which the execution occurred an NOP instruction, and also
makes FPU instructions (excluding FCMP instructions) from occurrence of the execution to the
instruction that accepts the exception NOP instructions. Consequently, FPU registers are not
updated by instructions during this interval.
With FPU-related CPU instructions, as above, FPU registers are not updated (NOP operation is
performed), but CPU registers are updated.
CPU instructions are not made NOP instructions, and operate as usual.
FPU exception
handling
Next instruction
Instruction after next
Branch destination
↔ ↔ ↔ ↔ ↔ ↔ ↔ Slots
IF
IF
⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅
ID
IF
EX
⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅
EX
MA
MA
Rev. 3.00 Jul 08, 2005 page 447 of 484
MA
IF
Section 8 Pipeline Operation
ID
REJ09B0051-0300