R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 66

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 5 Instruction Set
Classification
Branch
instructions
System control
instructions
Rev. 3.00 Jul 08, 2005 page 50 of 484
REJ09B0051-0300
Instruction
Type
10
14
Op Code
BF
BT
BRA
BRAF
BSR
BSRF
JMP
JSR
RTS
RTV/N
CLRT
CLRMAC
LDBANK
LDC
LDS
NOP
RESBANK
RTE
SETT
SLEEP
STBANK
STC
STS
TRAPA
Function
Conditional branch, delayed
conditional branch (branches if T = 0)
Conditional branch, delayed
conditional branch (branches if T = 1)
Unconditional delayed branch
Unconditional delayed branch
Delayed branch to subroutine
procedure
Delayed branch to subroutine
procedure
Unconditional delayed branch
Branch to subroutine procedure,
delayed branch to subroutine
procedure
Return from subroutine procedure,
delayed return from subroutine
procedure
Return from subroutine procedure with
Rm → R0 transfer
T bit clear
MAC register clear
Register restoration from specified
register bank entry
Load into control register
Load into system register
No operation
Register restoration from register bank
Return from exception handling
T bit setting
Transition to power-down state
Register save to specified register
bank entry
Store from control register
Store from system register
Trap exception handling
Number of
Instructions
15
36