R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 326

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 6 Instruction Descriptions
6.5.14
Description
This instruction inverts the most significant bit (sign bit) of the contents of floating-point register
FRn/DRn, and stores the result in FRn/DRn.
The cause and flag fields in FPSCR are not updated.
Operation
Possible Exceptions:
None
Rev. 3.00 Jul 08, 2005 page 310 of 484
REJ09B0051-0300
PR
0
1
void FNEG (int n){
}
/* Same operation is performed regardless of precision. */
Format
FNEG FRn
FNEG DRn
FR[n] = -FR[n];
pc += 2;
FNEG
Floating-Point
Sign Inversion
Abstract
-FRn → FRn
-DRn → DRn
Floating-point NEGate value
Code
1111nnnn01001101 1
1111nnn001001101 1
Floating-Point Instruction
Cycle
T Bit
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