R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 366

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 8 Pipeline Operation
8.3.7
The following rules apply to contention due to a branch instruction.
(1) Parallel execution is possible when the branch instruction does not branch.
(2) When a branch instruction is supplied as a succeeding instruction, parallel execution with the
(3) When a branch instruction is supplied as a preceding instruction, parallel execution with the
(4) For the delay slot, ID is performed in the next slot in which there is a branch instruction EX
(5) Execution of a delayed branch instruction is delayed if a fetch has not been performed for the
A relevant example is shown in figure 8.28.
Rev. 3.00 Jul 08, 2005 page 350 of 484
REJ09B0051-0300
ADD R3,R4
JMP @R2
Delay slot
Branch destination instruction
preceding instruction is possible regardless of the branching situation.
succeeding instruction is not possible if a branch occurs. Parallel execution is not possible
even if IF has already been completed for the delay slot (figure 8.32).
stage.
delay slot.
Details of Contention Due to Branch Instruction
Figure 8.32 Example of Contention between Branch Instructions
IF
IF
ID
ID
IF
EX
EX
—
ID
IF
ID
EX