R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 216

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 6 Instruction Descriptions
Example:
Note: When a delayed branch instruction is used, the branching operation takes place after the
Rev. 3.00 Jul 08, 2005 page 200 of 484
REJ09B0051-0300
JMP_TABLE: .data.l
TRGET:
slot instruction is executed, but the execution of instructions (register update, etc.) takes
place in the sequence delayed branch instruction → delayed slot instruction. For example,
even if a delayed slot instruction is used to change the register where the branch
destination address is stored, the register content previous to the change will be used as the
branch destination address.
MOV.L
JMP
MOV
.align
.................
ADD
JMP_TABLE,R0
@R0
R0,R1
4
TRGET
#1,R1
; Address of R0 = TRGET
; Branches to TRGET
; Executes MOV before branching
; Jump table
; ← Branch destination