R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 251

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

6.4.40
Format
NEGC
Description
Subtracts general register Rm data and the T bit from 0, and stores the result in Rn. If a borrow is
generated, T bit changes accordingly. This instruction is used for inverting the sign of a value that
has more than 32 bits.
Operation
Examples:
NEGC(long m,long n) /* NEGC Rm,Rn */
{
}
CLRT
NEGC
NEGC
unsigned long temp;
temp=0-R[m];
R[n]=temp-T;
if (0<temp)
else T=0;
if (temp<R[n])
PC+=2;
Rm,Rn
NEGC
Sign Inversion with Borrow
R1,R1
R0,R0
0 – Rm – T → Rn, Borrow → T
Abstract
; Sign inversion of R1 and R0 (64 bits)
; Before execution: R1 = H'00000001, T = 0
; After execution:
; Before execution: R0 = H'00000000, T = 1
; After execution:
T=1;
T=1;
NEGate with Carry
R1 = H'FFFFFFFF, T = 1
R0 = H'FFFFFFFF, T = 1
Code
0110nnnnmmmm1010
Rev. 3.00 Jul 08, 2005 page 235 of 484
Section 6 Instruction Descriptions
Arithmetic Instruction
Cycle
1
REJ09B0051-0300
T Bit
Borrow