LPC1114FHN33/203,5 NXP Semiconductors, LPC1114FHN33/203,5 Datasheet - Page 184

• Manufacturer Part Number: LPC1114FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 32 kB Fl 8 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1114FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1114
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
12.3 Register description
Table 172. Register overview: GPIO (base address port 0: 0x5000 0000; port 1: 0x5001 0000, port 2: 0x5002 0000;
UM10398
User manual
Name
GPIOnDATA
GPIOnDATA
-
GPIOnDIR
GPIOnIS
GPIOnIBE
GPIOnIEV
GPIOnIE
GPIOnRIS
GPIOnMIS
GPIOnIC
-
port 3: 0x5003 0000)
12.3.1 GPIO data register
Each GPIO register can be up to 12 bits wide and can be read or written using word or
half-word operations at word addresses.
The GPIOnDATA register holds the current logic state of the pin (HIGH or LOW),
independently of whether the pin is configured as an GPIO input or output or as another
digital function. If the pin is configured as GPIO output, the current value of the
GPIOnDATA register is driven to the pin.
Table 173. GPIOnDATA register (GPIO0DATA, address 0x5000 0000 to 0x5000 3FFC;
A read of the GPIOnDATA register always returns the current logic level (state) of the pin
independently of its configuration. Because there is a single data register for both the
value of the output driver and the state of the pin’s input, write operations have different
effects depending on the pin’s configuration:
Bit
11:0
31:12
•
•
All GPIO pins are inputs by default.
Reading and writing of data registers are masked by address bits 13:2.
Symbol
DATA
-
Access
R/W
R/W
-
R/W
R/W
R/W
R/W
R/W
R
R
W
-
GPIO1DATA, address 0x5001 0000 to 0x5001 3FFC; GPIO2DATA, address 0x5002
0000 to 0x5002 3FFC; GPIO3DATA, address 0x5003 0000 to 0x5003 3FFC) bit
description
All information provided in this document is subject to legal disclaimers.
0x0000 to 0x3FF8
0x3FFC
0x800C
Address offset
0x4000 to 0x7FFC
0x8000
0x8004
0x8008
0x8010
0x8014
0x8018
0x801C
0x8020 - 0xFFFF
Description
Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW =
0.
Reserved
Rev. 12 — 24 September 2012
Chapter 12: LPC111x/LPC11Cxx General Purpose I/O (GPIO)
Description
Port n data address masking register
locations for pins PIOn_0 to PIOn_11 (see
Section
Port n data register for pins PIOn_0 to
PIOn_11
reserved
Data direction register for port n
Interrupt sense register for port n
Interrupt both edges register for port n
Interrupt event register for port n
Interrupt mask register for port n
Raw interrupt status register for port n
Masked interrupt status register for port n
Interrupt clear register for port n
reserved
12.4.1).
UM10398
© NXP B.V. 2012. All rights reserved.
Reset
value
n/a
-
Access
R/W
-
Reset
value
n/a
n/a
-
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
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