LPC1114FHN33/203,5 NXP Semiconductors, LPC1114FHN33/203,5 Datasheet - Page 496

• Manufacturer Part Number: LPC1114FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 32 kB Fl 8 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1114FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1114
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
28.6 Peripherals
UM10398
User manual
28.5.7.12.2 Operation
28.5.7.12.3 Restrictions
28.5.7.12.4 Condition flags
28.5.7.12.5 Examples
28.6.1 About the ARM Cortex-M0
28.6.2 Nested Vectored Interrupt Controller
WFI
Remark: WFI is intended for power saving only. When writing software assume that WFI
might behave as a NOP operation.
There are no restrictions.
This instruction does not change the flags.
The address map of the Private peripheral bus (PPB) is:
Table 439. Core peripheral register regions
In register descriptions, the register type is described as follows:
RW — Read and write.
RO — Read-only.
WO — Write-only.
This section describes the Nested Vectored Interrupt Controller (NVIC) and the
registers it uses. The NVIC supports:
Address
0xE000E008-0xE000E00F
0xE000E010-0xE000E01F
0xE000E100-0xE000E4EF
0xE000ED00-0xE000ED3F
0xE000EF00-0xE000EF03
suspends execution until one of the following events occurs:
•
•
•
•
WFI ; Wait for interrupt
an exception
an interrupt becomes pending which would preempt if PRIMASK was clear
a Debug Entry request, regardless of whether debug is enabled.
32 interrupts.
Chapter 28: LPC111x/LPC11Cxx Appendix: ARM Cortex-M0 reference
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
Core peripheral
System Control Block
System timer
Nested Vectored Interrupt Controller
System Control Block
Nested Vectored Interrupt Controller
Description
Table 28–448
Table 28–457
Table 28–440
Table 28–448
Table 28–440
UM10398
© NXP B.V. 2012. All rights reserved.
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