LPC1114FHN33/203,5 NXP Semiconductors, LPC1114FHN33/203,5 Datasheet - Page 48

• Manufacturer Part Number: LPC1114FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 32 kB Fl 8 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1114FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1114
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
3.10 Deep-sleep mode details
UM10398
User manual
3.10.1 IRC oscillator
3.10.2 Start logic
3.10.3 Using the general purpose counter/timers to create a self-wake-up
The IRC is the only oscillator on the LPC111x/LPC11Cxx that can always shut down
glitch-free. Therefore it is recommended that the user switches the clock source to IRC
before the chip enters Deep-sleep mode.
The Deep-sleep mode is exited when the start logic indicates an interrupt to the ARM
core. The port pins PIO0_0 to PIO0_11 and PIO1_0 are connected to the start logic and
serve as wake-up pins. The user must program the start logic registers for each input to
set the appropriate edge polarity for the corresponding wake-up event. Furthermore, the
interrupts corresponding to each input must be enabled in the NVIC. Interrupts 0 to 12 in
the NVIC correspond to 13 PIO pins (see
The start logic does not require a clock to run because it uses the input signals on the
enabled pins to generate a clock edge when enabled. Therefore, the start logic signals
should be cleared (see
The start logic can also be used in Active mode to provide a vectored interrupt using the
LPC111x/LPC11Cxx’s input pins.
event
If enabled in Deep-sleep mode through the SYSAHBCLKCFG register, the counter/timers
can count clock cycles of the watchdog oscillator and create a match event when the
number of cycles equals a preset match value. The match event causes the
corresponding match output pin to go HIGH, LOW, or toggle. The state of the match
output pin is also monitored by the start logic and can trigger a wake-up interrupt if that pin
is enabled in the NVIC and the start logic trigger is configured accordingly in the start logic
edge control register (see
The following steps must be performed to configure the counter/timer and create a timed
Deep-sleep self-wake-up event:
1. Configure the port pin as match output in the IOCONFIG block. Select from pins
2. In the corresponding counter/timer, set the match value, and configure the match
3. Select the watchdog oscillator to run in Deep-sleep mode in the PDSLEEPCFG
4. Switch the clock source to the watchdog oscillator in the MAINCLKSEL register
5. Enable the pin, configure its edge detect function, and reset the start logic in the start
6. Disable all other peripherals in the SYSAHBCLKCTRL register.
7. Ensure that the DPDEN bit in the PCON register is set to zero
PIO0_1 or PIO0_8 to PIO0_11, which are inputs to the start logic and also hold a
match output function.
output for the selected pin.
register.
(Table
logic registers
18) and ensure the watchdog oscillator is powered in the PDRUNCFG register.
All information provided in this document is subject to legal disclaimers.
(Table 36
Rev. 12 — 24 September 2012
Chapter 3: LPC111x/LPC11Cxx System configuration (SYSCON)
Table
Table
to
38) before use.
Table
36).
39), and enable the interrupt in the NVIC.
Section
3.5.29).
(Table
UM10398
© NXP B.V. 2012. All rights reserved.
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