LPC1114FHN33/203,5 NXP Semiconductors, LPC1114FHN33/203,5 Datasheet - Page 31

• Manufacturer Part Number: LPC1114FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 32 kB Fl 8 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1114FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1114
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
3.5.15 SPI0 clock divider register
3.5.16 UART clock divider register
3.5.17 SPI1 clock divider register
Table 21.
This register configures the SPI0 peripheral clock SPI0_PCLK. The SPI0_PCLK can be
shut down by setting the DIV bits to 0x0.
Table 22.
This register configures the UART peripheral clock UART_PCLK. The UART_PCLK can
be shut down by setting the DIV bits to 0x0.
Remark: Note that for some parts the UART pins must be configured in the IOCON block
before the UART clock can be enabled.
Table 23.
This register configures the SPI1 peripheral clock SPI1_PCLK. The SPI1_PCLK can be
shut down by setting the DIV bits to 0x0.
Bit
17
18
31:19
Bit
7:0
31:8
Bit
7:0
31:8
Symbol
CAN
SSP1
-
Symbol
DIV
-
Symbol
DIV
-
System AHB clock control register (SYSAHBCLKCTRL, address 0x4004 8080) bit
description
SPI0 clock divider register (SSP0CLKDIV, address 0x4004 8094) bit description
UART clock divider register (UARTCLKDIV, address 0x4004 8098) bit description
All information provided in this document is subject to legal disclaimers.
SPI0_PCLK clock divider values
UART_PCLK clock divider values
Description
0: Disable SPI0_PCLK.
1: Divide by 1.
to
255: Divide by 255.
Reserved
Description
0: Disable UART_PCLK.
1: Divide by 1.
to
255: Divide by 255.
Reserved
Rev. 12 — 24 September 2012
Chapter 3: LPC111x/LPC11Cxx System configuration (SYSCON)
…continued
Value
0
1
0
1
-
Description
Enables clock for C_CAN. See
specific details.
Disable
Enable
Enables clock for SPI1.
Disable
Enable
Reserved
See
Section 3.1
for part specific details.
Section 3.1
UM10398
© NXP B.V. 2012. All rights reserved.
for part
Reset value
0x00
0x00
Reset value
0x00
0x00
31 of 538
Reset
value
0
0
0x00