LPC1114FHN33/203,5 NXP Semiconductors, LPC1114FHN33/203,5 Datasheet - Page 237

• Manufacturer Part Number: LPC1114FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 32 kB Fl 8 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1114FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1114
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
15.7.2 I
15.7.3 I
15.7.4 I
The AA bit can be cleared by writing 1 to the AAC bit in the CONCLR register. When AA is
0, a not acknowledge (HIGH level to SDA) will be returned during the acknowledge clock
pulse on the SCL line on the following situations:
Each I
Status register is Read-Only.
Table 220. I
The three least significant bits are always 0. Taken as a byte, the status register contents
represent a status code. There are 26 possible status codes. When the status code is
0xF8, there is no relevant information available and the SI bit is not set. All other 25 status
codes correspond to defined I
be set. For a complete list of status codes, refer to tables from
This register contains the data to be transmitted or the data just received. The CPU can
read and write to this register only while it is not in the process of shifting a byte, when the
SI bit is set. Data in DAT register remains stable as long as the SI bit is set. Data in DAT
register is always shifted from right to left: the first bit to be transmitted is the MSB (bit 7),
and after a byte has been received, the first bit of received data is located at the MSB of
the DAT register.
Table 221. I
This register is readable and writable and are only used when an I
slave mode. In master mode, this register has no effect. The LSB of the ADR register is
the General Call bit. When this bit is set, the General Call address (0x00) is recognized.
If this register contains 0x00, the I
registers (ADR0 to ADR3) will be cleared to this disabled state on reset. See also
Table
Bit
2:0
7:3
31:8 -
Bit
7:0
31:8 -
2
2
2
1. A data byte has been received while the I
2. A data byte has been received while the I
C Status register (I2C0STAT - 0x4000 0004)
C Data register (I2C0DAT - 0x4000 0008)
C Slave Address register 0 (I2C0ADR0- 0x4000 000C)
Symbol Description
Data
228.
-
Status
Symbol
2
C Status register reflects the condition of the corresponding I
2
2
C Status register (I2C0STAT - 0x4000 0004) bit description
C Data register (I2C0DAT - 0x4000 0008) bit description
This register holds data values that have been received or are to
be transmitted.
Reserved. The value read from a reserved bit is not defined.
All information provided in this document is subject to legal disclaimers.
Description
These bits are unused and are always 0.
These bits give the actual status information about the I
interface.
Reserved. The value read from a reserved bit is not defined.
Rev. 12 — 24 September 2012
2
C states. When any of these states entered, the SI bit will
2
C will not acknowledge any address on the bus. All four
Chapter 15: LPC111x/LPC11Cxx I2C-bus controller
2
2
C is in the master receiver mode.
C is in the addressed slave receiver mode.
Table 235
2
2
C
C interface is set to
2
C interface. The I
UM10398
© NXP B.V. 2012. All rights reserved.
to
Reset value
0
-
Table
Reset value
0
0x1F
-
237 of 538
240.
2
C