LPC1114FHN33/203,5 NXP Semiconductors, LPC1114FHN33/203,5 Datasheet - Page 497

• Manufacturer Part Number: LPC1114FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 32 kB Fl 8 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1114FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1114
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
Table 441. CMISIS access NVIC functions
[1]
UM10398
User manual
CMSIS function
void NVIC_EnableIRQ(IRQn_Type IRQn)
void NVIC_DisableIRQ(IRQn_Type IRQn)
void NVIC_SetPendingIRQ(IRQn_Type IRQn)
void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
uint32_t NVIC_GetPriority(IRQn_Type IRQn)
The input parameter IRQn is the IRQ number, see
28.6.2.1 Accessing the Cortex-M0 NVIC registers using CMSIS
28.6.2.2 Interrupt Set-enable Register
The processor automatically stacks its state on exception entry and unstacks this state on
exception exit, with no instruction overhead. This provides low latency exception handling.
The hardware implementation of the NVIC registers is:
Table 440. NVIC register summary
CMSIS functions enable software portability between different Cortex-M profile
processors.
To access the NVIC registers when using CMSIS, use the following functions:
The ISER enables interrupts, and shows which interrupts are enabled. See the register
summary in
The bit assignments are:
Address
0xE000E100
0xE000E180
0xE000E200
0xE000E280
0xE000E400-0xE
000E41C
•
•
•
•
A programmable priority level of 0-3 for each interrupt. A higher level corresponds to a
lower priority, so level 0 is the highest interrupt priority.
Level and pulse detection of interrupt signals.
Interrupt tail-chaining.
An external Non-Maskable Interrupt (NMI). See
the NMI for specific parts.
Table 440
Name
ISER
ICER
ISPR
ICPR
IPR0-7
[1]
Chapter 28: LPC111x/LPC11Cxx Appendix: ARM Cortex-M0 reference
[1]
All information provided in this document is subject to legal disclaimers.
[1]
[1]
Rev. 12 — 24 September 2012
[1]
Table 427
for the register attributes.
[1]
Type
RW
RW
RW
RW
RW
[1]
for more information.
Description
Enables an interrupt or exception.
Disables an interrupt or exception.
Sets the pending status of interrupt or exception to 1.
Clears the pending status of interrupt or exception to 0.
Reads the pending status of interrupt or exception.
This function returns non-zero value if the pending status is set
to 1.
Sets the priority of an interrupt or exception with configurable
priority level to 1.
Reads the priority of an interrupt or exception with configurable
priority level. This function returns the current priority level.
Reset value
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
Section 28.1
Description
Section 28–28.6.2.2
Section 28–28.6.2.3
Section 28–28.6.2.4
Section 28–28.6.2.5
Section 28–28.6.2.6
for implementation of
UM10398
© NXP B.V. 2012. All rights reserved.
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