LPC1114FHN33/203,5 NXP Semiconductors, LPC1114FHN33/203,5 Datasheet - Page 39

• Manufacturer Part Number: LPC1114FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 32 kB Fl 8 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1114FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1114
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
3.5.34 Wake-up configuration register
Table 41.
The bits in this register determine the state the chip enters when it is waking up from
Deep-sleep mode.
By default, the IRC and flash memory are powered and running and the BOD circuit is
enabled when the chip wakes up from Deep-sleep mode.
Remark: Reserved bits must be always written as indicated.
Table 42.
Bit
10:8
12:11
31:13
Bit
0
1
2
3
4
5
6
7
8
Symbol
NOTUSED
NOTUSED
-
Symbol
IRCOUT_PD
IRC_PD
FLASH_PD
BOD_PD
ADC_PD
SYSOSC_PD
WDTOSC_PD
SYSPLL_PD
-
Deep-sleep configuration register (PDSLEEPCFG, address 0x4004 8230) bit
description
Wake-up configuration register (PDAWAKECFG, address 0x4004 8234) bit
description
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
Chapter 3: LPC111x/LPC11Cxx System configuration (SYSCON)
…continued
Value
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Value
0
Description
IRC oscillator output wake-up configuration
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IRC oscillator power-down wake-up configuration
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Flash wake-up configuration
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BOD wake-up configuration
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ADC wake-up configuration
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System oscillator wake-up configuration
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Watchdog oscillator wake-up configuration
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System PLL wake-up configuration
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Reserved. Always write this bit as 1.
Description
Reserved. Always write these bits as 000.
Reserved. Always write these bits as 11.
Reserved
UM10398
© NXP B.V. 2012. All rights reserved.
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Reset
value
0
0
0
Reset
value
0
0
0
0
1
1
1
1
1