LPC1114FHN33/203,5 NXP Semiconductors, LPC1114FHN33/203,5 Datasheet - Page 350

• Manufacturer Part Number: LPC1114FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 32 kB Fl 8 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1114FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1114
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
19.7.12 PWM Control register (TMR16B0PWMC and TMR16B1PWMC)
Table 308. Count Control Register (TMR16B0CTCR - address 0x4000 C070 and
The PWM Control Register is used to configure the match outputs as PWM outputs. Each
match output can be independently set to perform either as PWM output or as match
output whose function is controlled by the External Match Register (EMR).
For timer 0, three single-edge controlled PWM outputs can be selected on the
CT16B0_MAT[2:0] outputs. For timer 1, two single-edged PWM outputs can be selected
on the CT16B1_Mat[1:0] outputs. One additional match register determines the PWM
cycle length. When a match occurs in any of the other match registers, the PWM output is
set to HIGH. The timer is reset by the match register that is configured to set the PWM
cycle length. When the timer is reset to zero, all currently HIGH match outputs configured
as PWM outputs are cleared.
Table 309. PWM Control Register (TMR16B0PWMC - address 0x4000 C074 and
Bit
7:5
31:8
Bit
0
1
2
Symbol
PWMEN0
PWMEN1
PWMEN2
Symbol
SELCC
-
TMR16B1CTCR - address 0x4001 0070) bit description
TMR16B1PWMC- address 0x4001 0074) bit description
All information provided in this document is subject to legal disclaimers.
Value
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
-
Value
0
1
0
1
0
1
Rev. 12 — 24 September 2012
Chapter 19: LPC1100XL series: 16-bit counter/timer CT16B0/1
Description
When bit 4 is one, these bits select which capture input edge
will cause the timer and prescaler to be cleared. These bits
have no effect when bit 4 is zero.
Rising Edge of CAP0 clears the timer (if bit 4 is set).
Falling Edge of CAP0 clears the timer (if bit 4 is set).
Rising Edge of CAP1 clears the timer (if bit 4 is set).
Falling Edge of CAP1 clears the timer (if bit 4 is set).
Reserved.
Reserved.
Reserved.
Reserved.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Description
PWM channel0 enable
CT16Bn_MAT0 is controlled by EM0.
PWM mode is enabled for CT16Bn_MAT0.
PWM channel1 enable
CT16Bn_MAT1 is controlled by EM1.
PWM mode is enabled for CT16Bn_MAT1.
PWM channel2 enable
Match channel 2 or pin CT16B0_MAT2 is controlled by
EM2. Match channel 2 is not pinned out on timer 1.
PWM mode is enabled for match channel 2 or pin
CT16B0_MAT2.
UM10398
© NXP B.V. 2012. All rights reserved.
Reset
value
0
0
0
350 of 538
Reset
value
0
-