LPC1114FHN33/203,5 NXP Semiconductors, LPC1114FHN33/203,5 Datasheet - Page 515

• Manufacturer Part Number: LPC1114FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 32 kB Fl 8 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1114FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1114
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
29.4 Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10. System PLL control register (SYSPLLCTRL,
Table 11. System PLL status register (SYSPLLSTAT,
Table 12. System oscillator control register (SYSOSCCTRL,
Table 13. Watchdog oscillator control register
Table 14. Internal resonant crystal control register
Table 15. System reset status register (SYSRSTSTAT,
Table 16. System PLL clock source select register
Table 17. System PLL clock source update enable register
Table 18. Main clock source select register (MAINCLKSEL,
Table 19. Main clock source update enable register
Table 20. System AHB clock divider register
Table 21. System AHB clock control register
Table 22. SPI0 clock divider register (SSP0CLKDIV,
Table 23. UART clock divider register (UARTCLKDIV,
Table 24. SPI1 clock divider register (SSP1CLKDIV,
Table 25. WDT clock source select register (WDTCLKSEL,
Table 26. WDT clock source update enable register
Table 27. WDT clock divider register (WDTCLKDIV, address
UM10398
User manual
LPC111x/LPC11Cxx feature changes. . . . . . . . .4
Ordering information . . . . . . . . . . . . . . . . . . . . .7
Ordering options . . . . . . . . . . . . . . . . . . . . . . . .9
LPC111x memory configuration . . . . . . . . . . . .16
LPC11Cxx memory configuration . . . . . . . . . . .16
Pin summary. . . . . . . . . . . . . . . . . . . . . . . . . . .20
Register overview: system control block (base
address 0x4004 8000) . . . . . . . . . . . . . . . . . .21
System memory remap register
(SYSMEMREMAP, address 0x4004 8000) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Peripheral reset control register (PRESETCTRL,
address 0x4004 8004) bit description. . . . . . . .23
address 0x4004 8008) bit description . . . . . . .24
address 0x4004 800C) bit description . . . . . . .25
address 0x4004 8020) bit description. . . . . . . .25
(WDTOSCCTRL, address 0x4004 8024) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
(IRCCTRL, address 0x4004 8028) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
address 0x4004 8030) bit description. . . . . . . .27
(SYSPLLCLKSEL, address 0x4004 8040) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
(SYSPLLCLKUEN, address 0x4004 8044) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
address 0x4004 8070) bit description. . . . . . . .28
(MAINCLKUEN, address 0x4004 8074) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
(SYSAHBCLKDIV, address 0x4004 8078) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
(SYSAHBCLKCTRL, address 0x4004 8080) bit
description
address 0x4004 8094) bit description. . . . . . . .31
address 0x4004 8098) bit description. . . . . . . .31
address 0x4004 809C) bit description . . . . . . .32
address 0x4004 80D0) bit description . . . . . . .32
(WDTCLKUEN, address 0x4004 80D4) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
. . . . . . . . . . . . . . . . . . . . . . . . . . .29
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
Table 28. CLKOUT clock source select register
Table 29. CLKOUT clock source update enable register
Table 30. CLKOUT clock divider registers
Table 31. POR captured PIO status registers 0
Table 32. POR captured PIO status registers 1
Table 33. BOD control register (BODCTRL, address 0x4004
Table 34. System tick timer calibration register
Table 35. NMI source selection register (NMISRC, address
Table 36. Start logic edge control register 0 (STARTAPRP0,
Table 37. Start logic signal enable register 0 (STARTERP0,
Table 38. Start logic reset register 0 (STARTRSRP0CLR,
Table 39. Start logic status register 0 (STARTSRP0,
Table 40. Allowed values for PDSLEEPCFG register . . . 38
Table 41. Deep-sleep configuration register
Table 42. Wake-up configuration register (PDAWAKECFG,
Table 43. Power-down configuration register (PDRUNCFG,
Table 44. Device ID register (DEVICE_ID, address 0x4004
Table 45. PLL frequency parameters. . . . . . . . . . . . . . . . 50
Table 46. PLL configuration examples. . . . . . . . . . . . . . . 51
Table 47. Flash configuration register (FLASHCFG, address
Table 48. Register overview: PMU (base address 0x4003
Table 49. Power control register (PCON, address 0x4003
Table 50. General purpose registers 0 to 3 (GPREG0 -
Table 51. General purpose register 4 (GPREG4, address
Table 52. set_pll routine . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 53. set_power routine . . . . . . . . . . . . . . . . . . . . . . 62
0x4004 80D8) bit description . . . . . . . . . . . . . . 33
(CLKOUTCLKSEL, address 0x4004 80E0) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
(CLKOUTUEN, address 0x4004 80E4) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
(CLKOUTCLKDIV, address 0x4004 80E8) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
(PIOPORCAP0, address 0x4004 8100) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
(PIOPORCAP1, address 0x4004 8104) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8150) bit description. . . . . . . . . . . . . . . . . . . . . 35
(SYSTCKCAL, address 0x4004 8154) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
0x4004 8174) bit description . . . . . . . . . . . . . . 36
address 0x4004 8200) bit description . . . . . . 36
address 0x4004 8204) bit description . . . . . . 37
address 0x4004 8208) bit description . . . . . . 37
address 0x4004 820C) bit description . . . . . . 37
(PDSLEEPCFG, address 0x4004 8230) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
address 0x4004 8234) bit description . . . . . . 39
address 0x4004 8238) bit description . . . . . . 40
83F4) bit description . . . . . . . . . . . . . . . . . . . . 42
0x4003 C010) bit description . . . . . . . . . . . . . . 52
8000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
8000) bit description . . . . . . . . . . . . . . . . . . . . 53
GPREG3, address 0x4003 8004 to 0x4003 8010)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 54
0x4003 8014) bit description . . . . . . . . . . . . . 54
Chapter 29: Supplementary information
UM10398
© NXP B.V. 2012. All rights reserved.
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