LPC1114FHN33/203,5 NXP Semiconductors, LPC1114FHN33/203,5 Datasheet - Page 511

• Manufacturer Part Number: LPC1114FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 32 kB Fl 8 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1114FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1114
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
Table 462. Cortex M0- instruction summary
Operation
Load
Store
Store
Push
Pop
Branch
Extend
Reverse
State change
Chapter 28: LPC111x/LPC11Cxx Appendix: ARM Cortex-M0 reference
All information provided in this document is subject to legal disclaimers.
Signed halfword to word
Description
Word, immediate offset
Halfword, immediate offset
Byte, immediate offset
Word, register offset
Halfword, register offset
Signed halfword, register offset
Byte, register offset
Signed byte, register offset
PC-relative
SP-relative
Multiple, excluding base
Multiple, including base
Word, immediate offset
Halfword, immediate offset
Byte, immediate offset
Word, register offset
Halfword, register offset
Byte, register offset
SP-relative
Multiple
Push
Push with link register
Pop
Pop and return
Conditional
Unconditional
With link
With exchange
With link and exchange
Signed byte to word
Unsigned halfword
Unsigned byte
Bytes in word
Bytes in both halfwords
Signed bottom half word
Supervisor Call
Disable interrupts
Enable interrupts
Read special register
Write special register
Rev. 12 — 24 September 2012
LDRSB Rd, [Rn, Rm]
STR Rd, [Rn, #<imm>]
SXTH Rd, Rm
Assembler
LDR Rd, [Rn, #<imm>]
LDRH Rd, [Rn, #<imm>]
LDRB Rd, [Rn, #<imm>]
LDR Rd, [Rn, Rm]
LDRH Rd, [Rn, Rm]
LDRSH Rd, [Rn, Rm]
LDRB Rd, [Rn, Rm]
LDR Rd, <label>
LDR Rd, [SP, #<imm>]
LDM Rn!, {<loreglist>}
LDM Rn, {<loreglist>}
STRH Rd, [Rn, #<imm>]
STRB Rd, [Rn, #<imm>]
STR Rd, [Rn, Rm]
STRH Rd, [Rn, Rm]
STRB Rd, [Rn, Rm]
STR Rd, [SP, #<imm>]
STM Rn!, {<loreglist>}
PUSH {<loreglist>}
PUSH {<loreglist>, LR}
POP {<loreglist>}
POP {<loreglist>, PC}
B<cc> <label>
B <label>
BL <label>
BX Rm
BLX Rm
SXTB Rd, Rm
UXTH Rd, Rm
UXTB Rd, Rm
REV Rd, Rm
REV16 Rd, Rm
REVSH Rd, Rm
SVC <imm>
CPSID i
CPSIE i
MRS Rd, <specreg>
MSR <specreg>, Rn
UM10398
© NXP B.V. 2012. All rights reserved.
2
2
2
2
2
2
1
Cycles
2
2
2
2
2
2
2
1 + N
1 + N
2
2
2
2
1 + N
1 + N
1 + N
1 + N
4 + N
1 or 3
3
4
3
3
1
1
1
1
1
1
-
1
1
4
4
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