LPC1114FHN33/203,5 NXP Semiconductors, LPC1114FHN33/203,5 Datasheet - Page 397

• Manufacturer Part Number: LPC1114FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 32 kB Fl 8 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1114FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1114
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
24.5 Register description
Table 356. Register overview: SysTick timer (base address 0xE000 E000)
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UM10398
User manual
Name
SYST_CSR
SYST_RVR
SYST_CVR
SYST_CALIB
Reset Value reflects the data stored in used bits only. It does not include content of reserved bits.
24.5.1 System Timer Control and status register
Access
R/W
R/W
R/W
R/W
Since the SysTick timer is a part of the Cortex-M0, it facilitates porting of software by
providing a standard timer that is available on Cortex-M0 based devices. The SysTick
timer can be used for:
Refer to the Cortex-M0 User Guide for details.
The systick timer registers are located on the ARM Cortex-M0 private peripheral bus (see
Figure
Section
The SYST_CSR register contains control information for the SysTick timer and provides a
status flag. This register is part of the ARM Cortex-M0 core system timer register block.
For a bit description of this register, see
This register determines the clock source for the system tick timer.
•
•
•
•
An RTOS tick timer which fires at a programmable rate (for example 100 Hz) and
invokes a SysTick routine.
A high-speed alarm timer using the core clock.
A simple counter. Software can use this to measure time to completion and time used.
An internal clock source control based on missing/meeting durations. The
COUNTFLAG bit-field in the control and status register can be used to determine if an
action completed within a set duration, as part of a dynamic clock management
control loop.
Address
offset
0x010
0x014
0x018
0x01C
97), and are part of the ARM Cortex-M0 core peripherals. For details, see
28.6.4.
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
Description
System Timer Control and status register
System Timer Reload value register
System Timer Current value register
System Timer Calibration value register
Chapter 24: LPC111x/LPC11Cxx System tick timer (SysTick)
Section 28.6.4 “System timer,
UM10398
SysTick”.
© NXP B.V. 2012. All rights reserved.
Reset value
0x000 0000
0
0
0x4
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