LPC1114FHN33/203,5 NXP Semiconductors, LPC1114FHN33/203,5 Datasheet - Page 240

• Manufacturer Part Number: LPC1114FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 32 kB Fl 8 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1114FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1114
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
15.7.7.1 Interrupt in Monitor mode
Table 227. I
[1]
Remark: The ENA_SCL and MATCH_ALL bits have no effect if the MM_ENA is ‘0’ (i.e. if
the module is NOT in monitor mode).
All interrupts will occur as normal when the module is in monitor mode. This means that
the first interrupt will occur when an address-match is detected (any address received if
the MATCH_ALL bit is set, otherwise an address matching one of the four address
registers).
Subsequent to an address-match detection, interrupts will be generated after each data
byte is received for a slave-write transfer, or after each byte that the module “thinks” it has
transmitted for a slave-read transfer. In this second case, the data register will actually
contain data transmitted by some other slave on the bus which was actually addressed by
the master.
Bit
0
1
2
31:3 -
When the ENA_SCL bit is cleared and the I
time becomes important. To give the part more time to respond to an I
DATA _BUFFER register is used
time.
Symbol
MM_ENA
ENA_SCL
MATCH_ALL
2
C Monitor mode control register (I2C0MMCTRL - 0x4000 001C) bit description
All information provided in this document is subject to legal disclaimers.
Value Description
0
1
0
1
0
1
-
Rev. 12 — 24 September 2012
Monitor mode enable.
Monitor mode disabled.
The I
SDA output will be forced high. This will prevent the I
module from outputting data of any kind (including ACK)
onto the I
Depending on the state of the ENA_SCL bit, the output may
be also forced high, preventing the module from having
control over the I
SCL output enable.
When this bit is cleared to ‘0’, the SCL output will be forced
high when the module is in monitor mode. As described
above, this will prevent the module from having any control
over the I
When this bit is set, the I
control over the clock line that it would in normal operation.
This means that, acting as a slave peripheral, the I
module can “stretch” the clock line (hold it low) until it has
had time to respond to an I
Select interrupt register match.
When this bit is cleared, an interrupt will only be generated
when a match occurs to one of the (up-to) four address
registers described above. That is, the module will respond
as a normal slave as far as address-recognition is
concerned.
When this bit is set to ‘1’ and the I
interrupt will be generated on ANY address received. This
will enable the part to monitor all traffic on the bus.
Reserved. The value read from reserved bits is not defined.
(Section
2
C module will enter monitor mode. In this mode the
2
2
Chapter 15: LPC111x/LPC11Cxx I2C-bus controller
C data bus.
C clock line.
15.7.9) to hold received data for a full 9-bit word transmission
2
C no longer has the ability to stall the bus, interrupt response
2
C clock line.
2
C module may exercise the same
2
C interrupt.
2
C is in monitor mode, an
2
C interrupt under these conditions, a
[1]
UM10398
© NXP B.V. 2012. All rights reserved.
2
C
2
C
240 of 538
Reset
value
0
0
0