LPC1114FHN33/203,5 NXP Semiconductors, LPC1114FHN33/203,5 Datasheet - Page 468

• Manufacturer Part Number: LPC1114FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 32 kB Fl 8 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1114FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1114
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
Fig 102. ASR #3
28.5.3.3.1 ASR
28.5.3.3.2 LSR
28.5.3.3 Shift Operations
Remark: When you update the PC with a BX, BLX, or POP instruction, bit[0] of any
address must be 1 for correct execution. This is because this bit indicates the destination
instruction set, and the Cortex-M0 processor only supports Thumb instructions. When a
BL or BLX instruction writes the value of bit[0] into the LR it is automatically assigned the
value 1.
Register shift operations move the bits in a register left or right by a specified number of
bits, the shift length. Register shift can be performed directly by the instructions ASR,
LSR, LSL, and ROR and the result is written to a destination register.The permitted shift
lengths depend on the shift type and the instruction, see the individual instruction
description. If the shift length is 0, no shift occurs. Register shift operations update the
carry flag except when the specified shift length is 0. The following sub-sections describe
the various shift operations and how they affect the carry flag. In these descriptions, Rm is
the register containing the value to be shifted, and n is the shift length.
Arithmetic shift right by n bits moves the left-hand 32 -n bits of the register Rm, to the right
by n places, into the right-hand 32 -n bits of the result, and it copies the original bit[31] of
the register into the left-hand n bits of the result. See
You can use the ASR operation to divide the signed value in the register Rm by 2
the result being rounded towards negative-infinity.
When the instruction is ASRS the carry flag is updated to the last bit shifted out, bit[n-1], of
the register Rm.
Remark:
Logical shift right by n bits moves the left-hand 32-n bits of the register Rm, to the right by
n places, into the right-hand 32 -n bits of the result, and it sets the left-hand n bits of the
result to 0. See
•
•
If n is 32 or more, then all the bits in the result are set to the value of bit[31] of Rm.
If n is 32 or more and the carry flag is updated, it is updated to the value of bit[31] of
Rm.
Chapter 28: LPC111x/LPC11Cxx Appendix: ARM Cortex-M0 reference
All information provided in this document is subject to legal disclaimers.
Figure
Rev. 12 — 24 September 2012
103.
Figure
28–102.
UM10398
© NXP B.V. 2012. All rights reserved.
468 of 538
n
, with