LPC1114FHN33/203,5 NXP Semiconductors, LPC1114FHN33/203,5 Datasheet - Page 218

• Manufacturer Part Number: LPC1114FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 32 kB Fl 8 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1114FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1114
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
14.5 Pin description
UM10398
User manual
The LPC111x/LPC11Cxx has two SPI/Synchronous Serial Port controllers.
Table 205. SPI pin descriptions
Remark: The SCK0 function is multiplexed to three different pin locations (two locations
on the HVQFN package). Use the IOCON_LOC register (see
physical location for the SCK0 function in addition to selecting the function in the IOCON
registers. The SCK1 pin is not multiplexed.
Pin
name
SCK0/1
SSEL0/1 I/O
MISO0/1 I/O
MOSI0/1 I/O
Type
I/O
All information provided in this document is subject to legal disclaimers.
Interface pin
name/function
SPI
SCK
SSEL FS
MISO DR(M)
MOSI DX(M)
Rev. 12 — 24 September 2012
SSI
CLK
DX(S)
DR(S)
Microwire
SK
CS
SI(M)
SO(S)
SO(M)
SI(S)
Chapter 14: LPC111x/LPC11Cxx SPI0/1 with SSP
Pin description
Serial Clock. SCK/CLK/SK is a clock signal used
to synchronize the transfer of data. It is driven by
the master and received by the slave. When
SPI/SSP interface is used, the clock is
programmable to be active-high or active-low,
otherwise it is always active-high. SCK only
switches during a data transfer. Any other time, the
SPI/SSP interface either holds it in its inactive state
or does not drive it (leaves it in high-impedance
state).
Frame Sync/Slave Select. When the SPI/SSP
interface is a bus master, it drives this signal to an
active state before the start of serial data and then
releases it to an inactive state after the data has
been sent.The active state of this signal can be
high or low depending upon the selected bus and
mode. When the SPI/SSP interface is a bus slave,
this signal qualifies the presence of data from the
Master according to the protocol in use.
When there is just one bus master and one bus
slave, the Frame Sync or Slave Select signal from
the Master can be connected directly to the slave’s
corresponding input. When there is more than one
slave on the bus, further qualification of their Frame
Select/Slave Select inputs will typically be
necessary to prevent more than one slave from
responding to a transfer.
Master In Slave Out. The MISO signal transfers
serial data from the slave to the master. When the
SPI/SSP is a slave, serial data is output on this
signal. When the SPI/SSP is a master, it clocks in
serial data from this signal. When the SPI/SSP is a
slave and is not selected by FS/SSEL, it does not
drive this signal (leaves it in high-impedance state).
Master Out Slave In. The MOSI signal transfers
serial data from the master to the slave. When the
SPI/SSP is a master, it outputs serial data on this
signal. When the SPI/SSP is a slave, it clocks in
serial data from this signal.
Section
UM10398
7.4) to select a
© NXP B.V. 2012. All rights reserved.
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