LPC1114FHN33/203,5 NXP Semiconductors, LPC1114FHN33/203,5 Datasheet - Page 333

• Manufacturer Part Number: LPC1114FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 32 kB Fl 8 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1114FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1114
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
Table 290. External Match Register (TMR16B0EMR - address 0x4000 C03C and TMR16B1EMR - address
UM10398
User manual
Bit
0
1
2
3
5:4
7:6
Symbol
EM0
EM1
EM2
EM3
EMC0
EMC1
0x4001 003C) bit description
18.7.10 External Match Register (TMR16B0EMR and TMR16B1EMR)
Value
0x0
0x1
0x2
0x3
0x0
0x1
0x2
0x3
The External Match Register provides both control and status of the external match
channels and external match pins CT16B0_MAT[2:0] and CT16B1_MAT[1:0].
If the match outputs are configured as PWM output in the PWMCON registers
(Section
rules
Description
External Match 0. This bit reflects the state of output CT16B0_MAT0/CT16B1_MAT0,
whether or not this output is connected to its pin. When a match occurs between the TC
and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4]
control the functionality of this output. This bit is driven to the
CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON
registers (0 = LOW, 1 = HIGH).
External Match 1. This bit reflects the state of output CT16B0_MAT1/CT16B1_MAT1,
whether or not this output is connected to its pin. When a match occurs between the TC
and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6]
control the functionality of this output. This bit is driven to the
CT16B0_MAT1/CT16B1_MAT1 pins if the match function is selected in the IOCON
registers (0 = LOW, 1 = HIGH).
External Match 2. This bit reflects the state of output match channel 2, whether or not
this output is connected to its pin. When a match occurs between the TC and MR2, this
bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the
functionality of this output. Note that on counter/timer 0 this match channel is not pinned
out. This bit is driven to the CT16B1_MAT2 pin if the match function is selected in the
IOCON registers (0 = LOW, 1 = HIGH).
External Match 3. This bit reflects the state of output of match channel 3. When a match
occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do
nothing. Bits EMR[11:10] control the functionality of this output. There is no output pin
available for this channel on either of the 16-bit timers.
External Match Control 0. Determines the functionality of External Match 0.
Do Nothing.
Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if
pinned out).
Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if
pinned out).
Toggle the corresponding External Match bit/output.
External Match Control 1. Determines the functionality of External Match 1.
Do Nothing.
Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if
pinned out).
Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if
pinned out).
Toggle the corresponding External Match bit/output.
(Section 18.7.13 “Rules for single edge controlled PWM outputs” on page
18.7.12), the function of the external match registers is determined by the PWM
Chapter 18: LPC1100/LPC1100C/LPC1100L series: 16-bit counter/timer
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
UM10398
© NXP B.V. 2012. All rights reserved.
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Reset
value
0
0
0
0
00
00