LPC1114FHN33/203,5 NXP Semiconductors, LPC1114FHN33/203,5 Datasheet - Page 337

• Manufacturer Part Number: LPC1114FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 32 kB Fl 8 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1114FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1114
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
18.8 Example timer operation
UM10398
User manual
Fig 69. A timer cycle in which PR=2, MRx=6, and both interrupt and reset on match are enabled
Fig 70. A timer cycle in which PR=2, MRx=6, and both interrupt and stop on match are enabled
prescale counter
timer counter
(counter enable)
timer counter
prescale
interrupt
counter
counter
PCLK
timer
reset
interrupt
TCR[0]
PCLK
Figure 69
The prescaler is set to 2 and the match register set to 6. At the end of the timer cycle
where the match occurs, the timer count is reset. This gives a full length cycle to the
match value. The interrupt indicating that a match occurred is generated in the next clock
after the timer reached the match value.
Figure 70
prescaler is again set to 2 and the match register set to 6. In the next clock after the timer
reaches the match value, the timer enable bit in TCR is cleared, and the interrupt
indicating that a match occurred is generated.
Fig 68. Sample PWM waveforms with a PWM cycle length of 100 (selected by MR3) and
4
2
4
2
MAT3:0 enabled as PWM outputs by the PWCON register.
shows a timer configured to reset the count and generate an interrupt on match.
shows a timer configured to stop and generate an interrupt on match. The
0
0
PWM2/MAT2
PWM1/MAT1
PWM0/MAT0
Chapter 18: LPC1100/LPC1100C/LPC1100L series: 16-bit counter/timer
All information provided in this document is subject to legal disclaimers.
1
5
1
5
1
Rev. 12 — 24 September 2012
2
2
0
0
0
1
6
6
0
41
2
0
65
1
0
2
(counter is reset)
100
0
MR2 = 100
MR1 = 41
MR0 = 65
UM10398
1
© NXP B.V. 2012. All rights reserved.
1
337 of 538