LPC1114FHN33/203,5 NXP Semiconductors, LPC1114FHN33/203,5 Datasheet - Page 380

• Manufacturer Part Number: LPC1114FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 32 kB Fl 8 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1114FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1114
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
21.8 Functional description
UM10398
User manual
Fig 80. A timer cycle in which PR=2, MRx=6, and both interrupt and reset on match are enabled
timer counter
21.8.1 Example timer operation
prescale
interrupt
counter
counter
PCLK
timer
reset
Table 341: PWM Control Register (TMR32B0PWMC - 0x4001 4074 and TMR32B1PWMC -
Figure 80
The prescaler is set to 2 and the match register set to 6. At the end of the timer cycle
where the match occurs, the timer count is reset. This gives a full length cycle to the
match value. The interrupt indicating that a match occurred is generated in the next clock
after the timer reached the match value.
Figure 81
prescaler is again set to 2 and the match register set to 6. In the next clock after the timer
reaches the match value, the timer enable bit in TCR is cleared, and the interrupt
indicating that a match occurred is generated.
Bit
3
31:4
4
2
Symbol
PWMEN3
-
shows a timer configured to reset the count and generate an interrupt on match.
shows a timer configured to stop and generate an interrupt on match. The
0
0x4001 8074) bit description
All information provided in this document is subject to legal disclaimers.
1
5
Value
0
1
Rev. 12 — 24 September 2012
2
Chapter 21: LPC1100XL series: 32-bit counter/timer CT32B0/1
Description
PWM channel 3 enable
Note: It is recommended to use match channel 3 to set
the PWM cycle.
CT32Bn_MAT3 is controlled by EM3.
PWM mode is enabled for CT32Bn_MAT3.
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
0
1
6
2
0
1
0
2
0
UM10398
1
© NXP B.V. 2012. All rights reserved.
1
Reset
value
0
NA
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