LPC1114FHN33/203,5 NXP Semiconductors, LPC1114FHN33/203,5 Datasheet - Page 264

• Manufacturer Part Number: LPC1114FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 32 kB Fl 8 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1114FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1114
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
Table 241. Miscellaneous States
UM10398
User manual
Status
Code
(STAT)
0xF8
0x00
15.10.6.1 Simultaneous Repeated START conditions from two masters
Status of the I
and hardware
No relevant state
information available;
SI = 0.
Bus error during MST
or selected slave
modes, due to an
illegal START or
STOP condition. State
0x00 can also occur
when interference
causes the I
to enter an undefined
state.
15.10.6 Some special cases
2
causes the I
clear the STO flag (no other bits in CON are affected). The SDA and SCL lines are
released (a STOP condition is not transmitted).
The I
during a serial transfer:
A Repeated START condition may be generated in the master transmitter or master
receiver modes. A special case occurs if another master simultaneously generates a
Repeated START condition (see
either master since they were both transmitting the same data.
If the I
generating a Repeated START condition itself, it will release the bus, and no interrupt
request is generated. If another master frees the bus by generating a STOP condition, the
I
serial data transfer can commence.
C block
2
•
•
•
•
•
C block will transmit a normal START condition (state 0x08), and a retry of the total
2
C-bus
Simultaneous Repeated START conditions from two masters
Data transfer after loss of arbitration
Forced access to the I
I
Bus error
2
2
C-bus obstructed by a LOW level on SCL or SDA
C hardware has facilities to handle the following special cases that may occur
2
C hardware detects a Repeated START condition on the I
Application software response
To/From DAT
No DAT action
No DAT action
2
C block to enter the “not addressed” slave mode (a defined state) and to
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
2
C-bus
To CON
STA STO SI
0
No CON action
Figure
1
Chapter 15: LPC111x/LPC11Cxx I2C-bus controller
0
57). Until this occurs, arbitration is not lost by
AA
X
Next action taken by I
Wait or proceed current transfer.
Only the internal hardware is affected in
the MST or addressed SLV modes. In all
cases, the bus is released and the I
block is switched to the not addressed
SLV mode. STO is reset.
2
C-bus before
UM10398
© NXP B.V. 2012. All rights reserved.
2
C hardware
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2
C