LPC1114FHN33/203,5 NXP Semiconductors, LPC1114FHN33/203,5 Datasheet - Page 381

• Manufacturer Part Number: LPC1114FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 32 kB Fl 8 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1114FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1114
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
Fig 81. A timer cycle in which PR=2, MRx=6, and both interrupt and stop on match are enabled
prescale counter
21.8.2 Rules for single edge controlled PWM outputs
(counter enable)
timer counter
interrupt
TCR[0]
PCLK
Note: When the match outputs are selected to function as PWM outputs, the timer reset
(MRnR) and timer stop (MRnS) bits in the Match Control Register MCR must be set to 0
except for the match register setting the PWM cycle length. For this register, set the
MRnR bit to 1 to enable the timer reset when the timer value matches the value of the
corresponding match register.
1. All single edge controlled PWM outputs go LOW at the beginning of each PWM cycle
2. Each PWM output will go HIGH when its match value is reached. If no match occurs
3. If a match value larger than the PWM cycle length is written to the match register, and
4. If a match register contains the same value as the timer reset value (the PWM cycle
5. If a match register is set to zero, then the PWM output will go to HIGH the first time the
Fig 82. Sample PWM waveforms with a PWM cycle length of 100 (selected by MR3) and
(timer is set to zero) unless their match value is equal to zero.
(i.e. the match value is greater than the PWM cycle length), the PWM output remains
continuously LOW.
the PWM signal is HIGH already, then the PWM signal will be cleared with the start of
the next PWM cycle.
length), then the PWM output will be reset to LOW on the next clock tick after the
timer reaches the match value. Therefore, the PWM output will always consist of a
one clock tick wide positive pulse with a period determined by the PWM cycle length
(i.e. the timer reload value).
timer goes back to zero and will stay HIGH continuously.
4
2
MAT3:0 enabled as PWM outputs by the PWMC register.
PWM2/MAT2
PWM1/MAT1
PWM0/MAT0
0
All information provided in this document is subject to legal disclaimers.
1
5
1
Rev. 12 — 24 September 2012
Chapter 21: LPC1100XL series: 32-bit counter/timer CT32B0/1
2
0
0
6
0
41
65
(counter is reset)
100
MR2 = 100
MR1 = 41
MR0 = 65
UM10398
© NXP B.V. 2012. All rights reserved.
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