LPC1114FHN33/203,5 NXP Semiconductors, LPC1114FHN33/203,5 Datasheet - Page 197

• Manufacturer Part Number: LPC1114FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 32 kB Fl 8 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1114FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1114
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
13.5.6 UART FIFO Control Register (U0FCR - 0x4000 8008, Write Only)
Table 190. UART Interrupt Handling
[1]
[2]
[3]
[4]
The UART THRE interrupt (U0IIR[3:1] = 001) is a third level interrupt and is activated
when the UART THR FIFO is empty provided certain initialization conditions have been
met. These initialization conditions are intended to give the UART THR FIFO a chance to
fill up with data to eliminate many THRE interrupts from occurring at system start-up. The
initialization conditions implement a one character delay minus the stop bit whenever
THRE = 1 and there have not been at least two characters in the U0THR at one time
since the last THRE = 1 event. This delay is provided to give the CPU time to write data to
U0THR without a THRE interrupt to decode and service. A THRE interrupt is set
immediately if the UART THR FIFO has held two or more characters at one time and
currently, the U0THR is empty. The THRE interrupt is reset when a U0THR write occurs or
a read of the U0IIR occurs and the THRE is the highest interrupt (U0IIR[3:1] = 001).
It is the lowest priority interrupt and is activated whenever there is any state change on
modem inputs pins, DCD, DSR or CTS. In addition, a low to high transition on modem
input RI will generate a modem interrupt. The source of the modem interrupt can be
determined by examining MSR[3:0]. A MSR read will clear the modem interrupt.
The U0FCR controls the operation of the UART RX and TX FIFOs.
U0IIR[3:0]
value
1100
0010
0000
Values “0000”, “0011”, “0101”, “0111”, “1000”, “1001”, “1010”, “1011”,”1101”,”1110”,”1111” are reserved.
For details see
For details see
Read Only)”
For details see
and
Only)”
[1]
Section 13.5.2 “UART Transmitter Holding Register (U0THR - 0x4000 8000 when DLAB = 0, Write
Priority Interrupt
Second Character
Third
Fourth
All information provided in this document is subject to legal disclaimers.
Section 13.5.9 “UART Line Status Register (U0LSR - 0x4000 8014, Read Only)”
Section 13.5.1 “UART Receiver Buffer Register (U0RBR - 0x4000 8000, when DLAB = 0,
Section 13.5.5 “UART Interrupt Identification Register (U0IIR - 0x4004 8008, Read Only)”
type
Time-out
indication
THRE
Modem
status
Rev. 12 — 24 September 2012
Interrupt source
Minimum of one character in the RX FIFO and no
character input or removed during a time period
depending on how many characters are in FIFO
and what the trigger level is set at (3.5 to 4.5
character times).
The exact time will be:
[(word length)  7 - 2]  8 + [(trigger level - number
of characters)  8 + 1] RCLKs
THRE
CTS or DSR or RI or DCD
[2]
Chapter 13: LPC111x/LPC11Cxx UART
UM10398
© NXP B.V. 2012. All rights reserved.
Interrupt
reset
U0RBR
Read
U0IIR
Read
source of
interrupt) or
THR write
MSR read
197 of 538
[3]
[4]
(if