LPC1114FHN33/203,5 NXP Semiconductors, LPC1114FHN33/203,5 Datasheet - Page 249

• Manufacturer Part Number: LPC1114FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 32 kB Fl 8 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1114FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1114
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
15.10 Details of I
UM10398
User manual
15.9.10 Status decoder and status register
15.9.8 Timing and control
15.9.9 Control register, CONSET and CONCLR
via the I
registers for details. The output clock pulses have a duty cycle as programmed unless the
bus is synchronizing with other SCL clock sources as described above.
The timing and control logic generates the timing and control signals for serial byte
handling. This logic block provides the shift pulses for DAT, enables the comparator,
generates and detects START and STOP conditions, receives and transmits
acknowledge bits, controls the master and slave modes, contains interrupt request logic,
and monitors the I
The I
and restart of a serial transfer, termination of a serial transfer, bit rate, address recognition,
and acknowledgment.
The contents of the I
set bits in the I
writing to CONCLR will clear bits in the I
value written.
The status decoder takes all of the internal status bits and compresses them into a 5-bit
code. This code is unique for each I
generate vector addresses for fast processing of the various service routines. Each
service routine processes a particular bus status. There are 26 possible bus states if all
four modes of the I
significant bits of the status register when the serial interrupt flag is set (by hardware) and
remains stable until the interrupt flag is cleared by software. The three least significant bits
of the status register are always zero. If the status code is used as a vector to service
routines, then the routines are displaced by eight address locations. Eight bytes of code is
sufficient for most of the service routines (see the software example in this section).
The four operating modes are:
Data transfers in each mode of operation are shown in
Figure
describing the I
•
•
•
•
2
C operating modes
Master Transmitter
Master Receiver
Slave Receiver
Slave Transmitter
2
C control register contains bits used to control the following I
56, and
2
C Clock Control Registers. See the description of the I2CSCLL and I2CSCLH
2
Figure
C control register that correspond to ones in the value written. Conversely,
2
All information provided in this document is subject to legal disclaimers.
C operating modes.
2
2
C-bus status.
C block are used. The 5-bit status code is latched into the five most
2
Rev. 12 — 24 September 2012
C control register may be read as CONSET. Writing to CONSET will
57.
Table 233
Chapter 15: LPC111x/LPC11Cxx I2C-bus controller
2
lists abbreviations used in these figures when
C-bus status. The 5-bit code may be used to
2
C control register that correspond to ones in the
Figure
53,
2
Figure
C block functions: start
UM10398
© NXP B.V. 2012. All rights reserved.
54,
Figure
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55,