LPC1114FHN33/203,5 NXP Semiconductors, LPC1114FHN33/203,5 Datasheet - Page 523

• Manufacturer Part Number: LPC1114FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 32 kB Fl 8 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1114FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1114
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
Table 419. Core register set summary. . . . . . . . . . . . . . .447
Table 420. PSR register combinations . . . . . . . . . . . . . .448
Table 421. APSR bit assignments . . . . . . . . . . . . . . . . . .449
Table 422. IPSR bit assignments. . . . . . . . . . . . . . . . . . .449
Table 423. EPSR bit assignments . . . . . . . . . . . . . . . . . .450
Table 424. PRIMASK register bit assignments . . . . . . . .450
Table 425. CONTROL register bit assignments . . . . . . .451
Table 426. Memory access behavior . . . . . . . . . . . . . . . .455
Table 427. Properties of different exception types. . . . . .457
Table 428. Exception return behavior . . . . . . . . . . . . . . .462
Table 429. Cortex-M0 instructions . . . . . . . . . . . . . . . . . .465
Table 430. CMSIS intrinsic functions to generate some
Table 431. CMSIS intrinsic functions to access the special
Table 432. Condition code suffixes . . . . . . . . . . . . . . . . .472
Table 433. Access instructions . . . . . . . . . . . . . . . . . . . .472
Table 434. Data processing instructions . . . . . . . . . . . . .478
Table 435. ADC, ADD, RSB, SBC and SUB operand
Table 436. Branch and control instructions . . . . . . . . . . .487
Table 437. Branch ranges . . . . . . . . . . . . . . . . . . . . . . . .488
Table 438. Miscellaneous instructions . . . . . . . . . . . . . . .489
Table 439. Core peripheral register regions . . . . . . . . . .496
Table 440. NVIC register summary . . . . . . . . . . . . . . . . .497
Table 441. CMISIS access NVIC functions . . . . . . . . . .497
Table 442. ISER bit assignments. . . . . . . . . . . . . . . . . . .498
Table 443. ICER bit assignments . . . . . . . . . . . . . . . . . .498
Table 444. ISPR bit assignments. . . . . . . . . . . . . . . . . . .498
Table 445. ICPR bit assignments . . . . . . . . . . . . . . . . . .499
Table 446. IPR bit assignments . . . . . . . . . . . . . . . . . . . .499
Table 447. CMSIS functions for NVIC control . . . . . . . . .501
Table 448. Summary of the SCB registers . . . . . . . . . . .502
Table 449. CPUID register bit assignments. . . . . . . . . . .502
Table 450. ICSR bit assignments . . . . . . . . . . . . . . . . . .503
Table 451. AIRCR bit assignments . . . . . . . . . . . . . . . . .505
Table 452. SCR bit assignments . . . . . . . . . . . . . . . . . . .505
Table 453. CCR bit assignments . . . . . . . . . . . . . . . . . . .506
Table 454. System fault handler priority fields . . . . . . . . .506
Table 455. SHPR2 register bit assignments . . . . . . . . . .507
Table 456. SHPR3 register bit assignments . . . . . . . . . .507
Table 457. System timer registers summary . . . . . . . . . .507
Table 458. SYST_CSR bit assignments . . . . . . . . . . . . .508
Table 459. SYST_RVR bit assignments . . . . . . . . . . . . .508
Table 460. SYST_CVR bit assignments . . . . . . . . . . . . .509
Table 461. SYST_CALIB register bit assignments . . . . .509
Table 462. Cortex M0- instruction summary . . . . . . . . . .510
Table 463. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . .513
UM10398
User manual
Cortex-M0 instructions . . . . . . . . . . . . . . . . . .466
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .467
restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . .480
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
Chapter 29: Supplementary information
UM10398
© NXP B.V. 2012. All rights reserved.
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