LPC1114FHN33/203,5 NXP Semiconductors, LPC1114FHN33/203,5 Datasheet - Page 402

• Manufacturer Part Number: LPC1114FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 32 kB Fl 8 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1114FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1114
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
Table 363. A/D Control Register (AD0CR - address 0x4001 C000) bit description
UM10398
User manual
Bit
7:0
15:8
16
19:17 CLKS
23:20 -
Symbol
SEL
CLKDIV
BURST
25.5.1 A/D Control Register (AD0CR - 0x4001 C000)
Value Description
0
1
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
The A/D Control Register provides bits to select A/D channels to be converted, A/D timing,
A/D modes, and the A/D start trigger.
Selects which of the AD7:0 pins is (are) to be sampled and converted. Bit 0 selects Pin
AD0, bit 1 selects pin AD1,..., and bit 7 selects pin AD7.
In software-controlled mode (BURST = 0), only one channel can be selected, i.e. only one
of these bits should be 1.
In hardware scan mode (BURST = 1), any numbers of channels can be selected, i.e any
or all bits can be set to 1. If all bits are set to 0, channel 0 is selected automatically (SEL =
0x01).
The APB clock (PCLK) is divided by CLKDIV +1 to produce the clock for the ADC, which
should be less than or equal to 4.5 MHz. Typically, software should program the smallest
value in this field that yields a clock of 4.5 MHz or slightly less, but in certain cases (such
as a high-impedance analog source) a slower clock may be desirable.
Burst mode
Remark: If BURST is set to 1, the ADGINTEN bit in the AD0INTEN register
must be set to 0.
Software-controlled mode: Conversions are software-controlled and require 11 clocks.
Hardware scan mode: The AD converter does repeated conversions at the rate selected
by the CLKS field, scanning (if necessary) through the pins selected by 1s in the SEL
field. The first conversion after the start corresponds to the least-significant bit set to 1 in
the SEL field, then the next higher bits (pins) set to 1 are scanned if applicable. Repeated
conversions can be terminated by clearing this bit, but the conversion in progress when
this bit is cleared will be completed.
Important: START bits must be 000 when BURST = 1 or conversions will not start.
This field selects the number of clocks used for each conversion in Burst mode, and the
number of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks
(10 bits) and 4 clocks (3 bits).
11 clocks / 10 bits
10 clocks / 9 bits
9 clocks / 8 bits
8 clocks / 7 bits
7 clocks / 6 bits
6 clocks / 5 bits
5 clocks / 4 bits
4 clocks / 3 bits
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
Chapter 25: LPC111x/LPC11Cxx ADC
(Table
UM10398
© NXP B.V. 2012. All rights reserved.
365)
402 of 538
Reset
Value
0x00
0
0
000
NA