LPC1114FHN33/203,5 NXP Semiconductors, LPC1114FHN33/203,5 Datasheet - Page 306

• Manufacturer Part Number: LPC1114FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 32 kB Fl 8 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1114FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1114
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
16.7.3.8 Configuration of a receive object
16.7.3.9 Handling of received messages
To prevent the reset of TXRQST at the end of a transmission that may already be in
progress while the data is updated, NEWDAT has to be set together with TXRQST. For
details see
When NEWDAT is set together with TXRQST, NEWDAT will be reset as soon as the new
transmission has started.
Table 276
Table
Table 276. Initialization of a receive object
The Arbitration Registers (ID28-0 and XTD bit) are given by the application. They define
the identifier and type of accepted received messages. If an 11-bit Identifier (“Standard
Frame”) is used, it is programmed to ID28 to ID18. ID17 to ID0 can then be disregarded.
When a Data Frame with an 11-bit Identifier is received, ID17 to ID0 will be set to ‘0’.
If the RxIE bit is set, the INTPND bit will be set when a received Data Frame is accepted
and stored in the Message Object.
The Data Length Code (DLC[3:0] is given by the application. When the Message Handler
stores a Data Frame in the Message Object, it will store the received Data Length Code
and eight data bytes. If the Data Length Code is less than 8, the remaining bytes of the
Message Object will be overwritten by non specified values.
The Mask Registers (Msk[28:0], UMASK, MXTD, and MDIR bits) may be used
(UMASK=’1’) to allow groups of Data Frames with similar identifiers to be accepted. For
details see section
applications.
The CPU may read a received message any time via the IFx Interface registers. The data
consistency is guaranteed by the Message Handler state machine.
To transfer the entire received message from message RAM into the message buffer,
software must write first 0x007F to the Command Mask Register and then the number of
the Message Object to the Command Request Register. Additionally, the bits NEWDAT
and INTPND are cleared in the Message RAM (not in the Message Buffer).
If the Message Object uses masks for acceptance filtering, the arbitration bits show which
of the matching messages has been received.
MSGVAL
MSGLST
1
0
253)
shows how a receive object should be initialized by software (see also
Section
Arbitration
application
dependent
application
dependent
All information provided in this document is subject to legal disclaimers.
RXIE
bits
Section
16.7.3.3.
Rev. 12 — 24 September 2012
application
dependent
Data bits
16.7.3.4.1. The DIR bit should not be masked in typical
TXIE
0
Chapter 16: LPC111x/LPC11Cxx C_CAN controller
application
dependent
Mask bits
INTPND
0
RMTEN
EOB
1
0
DIR
0
UM10398
TXRQST
© NXP B.V. 2012. All rights reserved.
0
NEWDAT
0
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