LPC1114FHN33/203,5 NXP Semiconductors, LPC1114FHN33/203,5 Datasheet - Page 24

• Manufacturer Part Number: LPC1114FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 32 kB Fl 8 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1114FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1114
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
3.5.3 System PLL control register
3.5.4 System PLL status register
Table 9.
This register connects and enables the system PLL and configures the PLL multiplier and
divider values. The PLL accepts an input frequency from 10 MHz to 25 MHz from various
clock sources. The input frequency is multiplied up to a high frequency, then divided down
to provide the actual clock used by the CPU, peripherals, and memories. The PLL can
produce a clock up to the maximum allowed for the CPU.
Table 10.
This register is a Read-only register and supplies the PLL lock status (see
Bit
1
2
3
31:4
Bit
4:0
6:5
31:7
Symbol
I2C_RST_N
SSP1_RST_N
CAN_RST_N
-
Symbol
MSEL
PSEL
-
Peripheral reset control register (PRESETCTRL, address 0x4004 8004) bit
description
System PLL control register (SYSPLLCTRL, address 0x4004 8008) bit description
All information provided in this document is subject to legal disclaimers.
Value
0x0
0x1
0x2
0x3
-
Rev. 12 — 24 September 2012
Chapter 3: LPC111x/LPC11Cxx System configuration (SYSCON)
Value
0
1
0
1
0
1
-
programmed MSEL value + 1.
00000: Division ratio M = 1
to
11111: Division ratio M = 32.
Post divider ratio P. The division ratio is 2  P.
P = 1
P = 2
P = 4
P = 8
Description
Feedback divider value. The division value M is the
Reserved. Do not write ones to reserved bits.
Description
I2C reset control
Resets the I2C peripheral.
I2C reset de-asserted.
SPI1 reset control
Resets the SPI1 peripheral.
SPI1 reset de-asserted.
C_CAN reset control. See
details.
Resets the C_CAN peripheral.
C_CAN reset de-asserted.
Reserved
Section 3.1
for part specific
UM10398
© NXP B.V. 2012. All rights reserved.
Section
24 of 538
3.11.1).
Reset
value
0
0
0
0x00
Reset
value
0x000
0x00
0x0