LPC1114FHN33/203,5 NXP Semiconductors, LPC1114FHN33/203,5 Datasheet - Page 58

• Manufacturer Part Number: LPC1114FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 32 kB Fl 8 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1114FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1114
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
5.5.1.1 Param0: system PLL input frequency and Param1: expected system clock
5.5.1.2 Param2: mode
The routine returns a result code that indicates if the system PLL was successfully set
(PLL_CMD_SUCCESS) or not (in which case the result code identifies what went wrong).
The current system frequency value is also returned. The application should use this
information to adjust other clocks in the device (the SSP, UART, and WDT clocks, and/or
clockout).
Table 52.
The following definitions are needed when making set_pll power routine calls:
/* set_pll mode options */
#define
#define
#define
#define
/* set_pll result0 options */
#define
#define
#define
#define
#define
For a simplified clock configuration scheme see
set_pll looks for a setup in which the system PLL clock does not exceed 50 MHz. It easily
finds a solution when the ratio between the expected system clock and the system PLL
input frequency is an integer value, but it can also find solutions in other cases.
The system PLL input frequency (Param0) must be between 10000 to 25000 kHz (10
MHz to 25 MHz) inclusive. The expected system clock (Param1) must be between 1 and
50000 kHz inclusive. If either of these requirements is not met, set_pll returns
PLL_INVALID_FREQ and returns Param0 as Result1 since the PLL setting is unchanged.
The first priority of set_pll is to find a setup that generates the system clock at exactly the
rate specified in Param1. If it is unlikely that an exact match can be found, input parameter
mode (Param2) should be used to specify if the actual system clock can be less than or
equal, greater than or equal or approximately the value specified as the expected system
clock (Param1).
A call specifying CPU_FREQ_EQU will only succeed if the PLL can output exactly the
frequency requested in Param1.
Routine
Input
Result
set_pll routine
CPU_FREQ_EQU
CPU_FREQ_LTE
CPU_FREQ_GTE
CPU_FREQ_APPROX
PLL_CMD_SUCCESS
PLL_INVALID_FREQ
PLL_INVALID_MODE
PLL_FREQ_NOT_FOUND
PLL_NOT_LOCKED
set_pll
Param0: system PLL input frequency (in kHz)
Param1: expected system clock (in kHz)
Param2: mode (CPU_FREQ_EQU, CPU_FREQ_LTE, CPU_FREQ_GTE,
CPU_FREQ_APPROX)
Param3: system PLL lock time-out
Result0: PLL_CMD_SUCCESS | PLL_INVALID_FREQ | PLL_INVALID_MODE |
PLL_FREQ_NOT_FOUND | PLL_NOT_LOCKED
Result1: system clock (in kHz)
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
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Chapter 5: LPC111x/LPC11Cxx Power profiles
Figure
12. For more details see
UM10398
© NXP B.V. 2012. All rights reserved.
Figure
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