LPC1114FHN33/203,5 NXP Semiconductors, LPC1114FHN33/203,5 Datasheet - Page 448

• Manufacturer Part Number: LPC1114FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 32 kB Fl 8 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1114FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1114
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
28.4.1.3.3 Link Register
28.4.1.3.4 Program Counter
28.4.1.3.5 Program Status Register
On reset, the processor loads the MSP with the value from address 0x00000000.
The Link Register (LR) is register R14. It stores the return information for subroutines,
function calls, and exceptions. On reset, the LR value is Unknown.
The Program Counter (PC) is register R15. It contains the current program address. On
reset, the processor loads the PC with the value of the reset vector, which is at address
0x00000004. Bit[0] of the value is loaded into the EPSR T-bit at reset and must be 1.
The Program Status Register (PSR) combines:
These registers are mutually exclusive bitfields in the 32-bit PSR. The PSR bit
assignments are:
Access these registers individually or as a combination of any two or all three registers,
using the register name as an argument to the MSR or MRS instructions. For example:
The PSR combinations and attributes are:
Table 420. PSR register combinations
[1]
[2]
Register
PSR
IEPSR
IAPSR
EAPSR
Fig 96. APSR, IPSR, EPSR register bit assignments
•
•
•
•
•
Application Program Status Register (APSR)
Interrupt Program Status Register (IPSR)
Execution Program Status Register (EPSR).
read all of the registers using PSR with the MRS instruction
write to the APSR using APSR with the MSR instruction.
The processor ignores writes to the IPSR bits.
Reads of the EPSR bits return zero, and the processor ignores writes to the these bits
Chapter 28: LPC111x/LPC11Cxx Appendix: ARM Cortex-M0 reference
All information provided in this document is subject to legal disclaimers.
Type
RW
RO
RW
RW
Rev. 12 — 24 September 2012
[1][2]
[1]
[2]
Combination
APSR, EPSR, and IPSR
EPSR and IPSR
APSR and IPSR
APSR and EPSR
UM10398
© NXP B.V. 2012. All rights reserved.
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