Z8F16800144ZCOG Zilog, Z8F16800144ZCOG Datasheet
Z8F16800144ZCOG
Specifications of Z8F16800144ZCOG
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Z8F16800144ZCOG Summary of contents
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... An Company High-Performance 8-Bit Microcontrollers Z8 Encore! XP Product Specification PS025011-1010 ® Copyright © 2010 by Zilog , Inc. All rights reserved. www.zilog.com ® F1680 Series ...
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... TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. The information contained within this document has been verified according to the general principles of electrical and mechanical engineering. Z8, Z8 Encore!, Z8 Encore! XP, Z8 Encore! MC, Crimzon, eZ80, and ZNEO are trademarks or registered trademarks of Zilog, Inc. All other product or service names are the property of their respective owners. PS025011-1010 ...
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... Table 194, Table 196, Table 199, Table 200, and Table 201. Added Updated Table 190. Changed description of Z8F16800144ZCOG Z8 Encore! XP Dual 44-pin F1680 Series Development Kit. Updated electrical characteristics in Table 189, Table 192, Table 193, Table 195, Table VBO_Trim section and table. ...
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Table of Contents Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Crystal Oscillator Override . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Operation in HALT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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LIN-UART Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Low-Power Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 Enhanced Serial Peripheral Interface ...
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I2C Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 ...
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... Trim Bit Address 0004H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 Trim Bit Address 0005H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 Trim Bit Address 0006H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 Trim Bit Address 0007H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 Trim Bit Address 0008H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 Zilog Calibration Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 Temperature Sensor Calibration Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 Non-Volatile Data Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 NVDS Code Interface ...
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OCDCNTR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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On-Chip Peripheral AC and DC Electrical Characteristics . . . . . . . . . . . . . . . 347 General Purpose I/O Port Input Data Sample Timing . . . . . . . . . ...
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... Additional two basic 16-bit timers with interrupt (shared as UART Baud Rate Generator) • Optional 16-bit Multi-Channel Timer which supports four Capture/Compare/PWM modules (44-pin packages only) PS025011-1010 Z8 Encore! XP F1680 Series MCU family is based on Zilog’s advanced 8-bit ® ® F1680 Series Product Specification 1 ...
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Watchdog Timer (WDT) with dedicated internal RC oscillator • General-Purpose Input/Output (GPIO) pins depending upon package • direct LED drives with programmable drive current capability • interrupt sources with up ...
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Block Diagram Figure 1 displays the block diagram of the architecture of Z8 Encore! XP F1680 Series devices. WDT with RC Oscillator Multichannel Timer Enhanced SPI Master/Slave 8 Channel 10-Bit A/D Converter 3 x 16-Bit Timer/PWM Temperature ...
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... CPU and Peripheral Overview eZ8 CPU Features Zilog’s eZ8 CPU, latest 8-bit CPU meets the continuing demand for faster and more code- efficient microcontrollers. It executes a superset of the original Z8 eZ8 CPU features include: • Direct register-to-register architecture allows each register to function as an accumulator, improving execution time and decreasing the required Program Memory. • ...
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Non-Volatile Data Storage The Non-Volatile Data Storage (NVDS) uses a hybrid hardware/software scheme to implement a byte-programmable data memory and is capable of over 100,000 write cycles. Internal Precision Oscillator The internal precision oscillator (IPO trimmable clock ...
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Low-Voltage Detector The low-voltage detector generates an interrupt when the supply voltage drops below a user-programmable level. Enhanced SPI The enhanced SPI is a full-duplex, buffered, synchronous character-oriented channel which supports a four-wire interface. UART with LIN A full-duplex 9-bit ...
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Multi-Channel Timer The multi-channel timer has a 16-bit up/down counter and a 4-channel Capture/Compare/ PWM channel array. This timer enables the support of multiple synchronous Capture/ Compare/PWM channels based on a single timer. Interrupt Controller The Z8 Encore! XP F1680 ...
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Acronyms and Expansions This document uses the following acronyms and expansions. Abbreviations/ Acronyms ADC NVDS LPO LIN SPI ESPI WDT GPIO OCD POR LVD VBO IPO UART IrDA PDIP SOIC SSOP QFN LQFP PRAM PC IRQ ISR ...
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Abbreviations/ Acronyms LSB PWM CI TI Endec TDM TTL SAR PS025011-1010 Z8 Encore! XP Expansions Least-significant byte Pulse-Width Modulation Channel Interrupt Timer Interrupt Encoder/Decoder Inter IC Sound Time division multiplexing Transistor-Transistor Logic Successive Approximation Register P R ...
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PS025011-1010 Z8 Encore ® F1680 Series Product Specification 10 Overview ...
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Pin Description Overview The Z8 Encore! XP F1680 Series products are available in a variety of package styles and pin configurations. This chapter describes the signals and available pin configurations for each of the package styles. For information on the ...
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PB1/ANA1/AMPINN PB2/ANA2/AMPINP PB3/CLKIN/ANA3 PA0/T0IN/T0OUT/XIN PA1/T0OUT/XOUT PA2/DE0/X2IN PA3/CTS0/X2OUT PA4/RXD0/IRRX0/T2IN/T2OUT Figure 2. Z8F2480, Z8F1680 and Z8F0880 in 20-Pin SOIC, SSOP or PDIP Packages PB2/ANA2/AMPINP PB4/ANA7 PB5/VREF PB3/CLKIN/ANA3 PA0/T0IN/T0OUT/XIN PA1/T0OUT/XOUT PA2/DE0/X2IN PA3/CTS0/X2OUT PA4/RXD0/IRRX0 PA5/TXD0/IRTX0 Figure 3. Z8F2480, Z8F1680 and Z8F0880 in 28-Pin SOIC, ...
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PB1/AMPINN/ANA1 PB2/AMPINP/ANA2 PB4/ANA7 PB5/VREF PB3/CLKIN/ANA3 PA0/T0IN/T0OUT/XIN PA1/T0OUT/XOUT PD7/C0OUT PA2/DE0/X2IN PA3/CTS0/X2OUT PA4/RXD0/IRRX0 PA5/TXD0/IRTX0 Figure 4. Z8F2480, Z8F1680 and Z8F0880 in 40-Pin Dual Inline Package (PDIP) PS025011-1010 1 40 PB0/AMPOUT/ANA0 PD1/C1INN PD2/C1INP PC3/MISO/LED 5 PC2/ANA6/SS/LED 35 PC1/ANA5/C0INN/LED PE0 AVDD PC0/ANA4/C0INP/LED VSS VDD ...
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PE6/T4CHD PE0/T4IN AVDD VDD PA0/T0IN/T0OUT/XIN PA1/T0OUT/XOUT VSS AVSS PE1/SCL PE2/SDA PD7/COUT0 Figure 5. Z8F2480, Z8F1680 and Z8F0880 in 44-Pin Low-Profile Quad Flat Package (LQFP) or Quad Flat No Lead (QFN) Signal Descriptions Table 3 on page 15 describes the Z8 ...
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Table 3. Signal Descriptions Signal Mnemonic I/O Description General-Purpose I/O Ports A–E PA[7:0] I/O Port A: These pins are used for general-purpose I/O. PB[5:0] I/O Port B: These pins are used for GPIO. PC[7:0] I/O Port C: These pins are ...
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Table 3. Signal Descriptions (Continued) Signal Mnemonic I/O Description Timers T0OUT/T1OUT/ O Timer Output 0–2: These signals are output from the timers. T2OUT Timer Complement Output 0–2: These signals are output from the T0OUT/T1OUT/ O T2OUT timers in PWM ...
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Table 3. Signal Descriptions (Continued) Signal Mnemonic I/O Description X2IN I Watch Crystal Input: This is the input pin to the low-power 32 kHz oscillator. A watch crystal can be connected between the X2IN and the X2OUT pin to form ...
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Table 4. Pin Characteristics (20-, 28-, 40- and 44-pin Devices) Symbol Direction Reset Mnemonic Direction AVDD N/A N/A AVSS N/A N/A DBG I/O I PA[7:0] I/O I PB[5:0] I/O I PC[7:0] I/O I PD[7:1] I/O I PE[6:0] I/O I PS025011-1010 ...
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Table 4. Pin Characteristics (20-, 28-, 40- and 44-pin Devices) (Continued) Symbol Direction Reset Mnemonic Direction RESET/PD0 I/O I/O (defaults to RESET) VDD N/A N/A VSS N/A N/A PS025011-1010 Internal Active Tristate Low or Output Pull-up or Active Pull-down ...
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PS025011-1010 Z8 Encore ® F1680 Series Product Specification 20 Pin Description ...
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... Data Memory These three address spaces are covered briefly in the following sections. For more details on the eZ8 CPU and its address space, refer to eZ8 CPU User Manual (UM0128) available for download at www.zilog.com. Register File The Register File address space in the Z8 Encore! Register File is composed of two sections: Control Registers and general-purpose registers ...
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Program RAM to shadow Interrupt Service Routines (ISR). For details, see PRAM_M user option bit on page 270. Program Memory The eZ8 CPU supports Program Memory address space. The Z8 Encore! XP F1680 Series ...
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Table 5. Z8 Encore! XP F1680 Series Program Memory Maps (Continued) Program Memory Address (Hex) 0002–0003 0004–0005 0006–0007 0008–0037 0038–003D 003E–3FFF E000–E3FF Z8F0880 Product 0000–0001 0002–0003 0004–0005 0006–0007 0008–0037 0038–003D 003E–1FFF E000–E3FF Note: *See Table 34 Data Memory The Z8 ...
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... FE60–FE7F FE80–FFFF PS025011-1010 Z8 Encore! XP Function Zilog Option Bits Part Number: 20-character ASCII alphanumeric code Left justified and filled with FH Reserved Zilog Calibration Data (only use the first two bytes FE60 and FE61) Reserved ® F1680 Series Product Specification 24 Address Space ...
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Register Map Table 7 provides the address map for the Register File of Z8 Encore! XP F1680 Series devices. Not all devices and package styles in the Z8 Encore! XP F1680 Series support the ADC or all of the GPIO ...
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Table 7. Register File Address Map (Continued) Address (Hex) Register Description F21 Timer 0 PWM1 Low Byte F22 Timer 0 Control 2 F23 Timer 0 Status F2C Timer 0 Noise Filter Control Timer 1 F08 Timer 1 High Byte F09 ...
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Table 7. Register File Address Map (Continued) Address (Hex) Register Description F2E Timer 2 Noise Filter Control F2F–F3F Reserved LIN UART 0 F40 LIN UART0 Transmit Data LIN UART0 Receive Data F41 LIN UART0 Status 0—Standard UART Mode LIN UART0 ...
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Table 7. Register File Address Map (Continued) Address (Hex) Register Description 2 F52 I C Control 2 F53 I C Baud Rate High Byte 2 F54 I C Baud Rate Low Byte 2 F55 I C State 2 F56 I ...
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Table 7. Register File Address Map (Continued) Address (Hex) Register Description F83 LED Drive Level High Bit F84 LED Drive Level Low Bit F85 Reserved Oscillator Control F86 Oscillator Control 0 F87 Oscillator Control 1 F88–F8F Reserved Comparator 0 F90 ...
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Table 7. Register File Address Map (Continued) Address (Hex) Register Description FC8 IRQ2 Enable Low Bit FC9–FCC Reserved FCD Interrupt Edge Select FCE Shared Interrupt Select FCF Interrupt Control GPIO Port A FD0 Port A Address FD1 Port A Control ...
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Table 7. Register File Address Map (Continued) Address (Hex) Register Description Reset FF0 Reset Status FF1 Reserved Watchdog Timer FF2 Watchdog Timer Reload High Byte FF3 Watchdog Timer Reload Low Byte FF4–FF5 Reserved Trim Bit Control FF6 Trim Bit Address ...
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PS025011-1010 Z8 Encore ® F1680 Series Product Specification 32 Register Map ...
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Reset, Stop Mode Recovery, and Low-Voltage Detection Overview The Reset Controller within the Z8 Encore! XP F1680 Series device controls Reset and Stop Mode Recovery operation and provides indication of low-voltage supply conditions. During the operation, the following events ...
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Table 8. Reset and STOP Mode Recovery Characteristics and Latency Reset Type Control Registers System Reset Reset (non-POR Reset) (as applicable) System Reset Reset (POR Reset) (as applicable) System Reset with Reset Crystal Oscillator ...
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Reset vector address. Because the control registers are reinitialized by a System Reset, the system clock after reset is always the 11 MHz IPO. User software must reconfigure the oscillator control block such that ...
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After power on, the POR circuit keeps idle until the supply voltage drops below V voltage. Figure 7 After the Z8 Encore! XP F1680 Series device exits the POR state, the eZ8 CPU fetches the Reset vector. Following this POR, ...
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V V CC(min) V POR POR (POR_DELAY) POR Reset Voltage Brownout Reset The Z8 Encore! XP F1680 Series provides a VBO Reset feature for low-voltage protection. The VBO circuit has a preset threshold voltage (V V ...
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VBO+ V VBO Program Execution WDT Clock System Clock Internal Reset Signal Internal VBO Reset VBO delay: pulse rejection Note: Not to Scale Figure 8. Voltage Brownout Reset Operation Watchdog Timer Reset If the ...
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A reset pulse three clock cycles in duration might trigger a Reset; a pulse four cycles in duration always ...
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Table 10 following provides more detailed information on each of the Stop Mode Recovery sources. Table 10. Stop Mode Recovery Sources and Resulting Action Operating Mode Stop Mode Recovery Source STOP mode Watchdog Timer timeout when ...
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Stop Mode Recovery Using Comparator Interrupt If Comparator enabled for STOP mode operation interrupts during STOP mode, the device undergoes a Stop Mode Recovery sequence. In the Reset Status Register, the set the Z8 Encore! XP F1680 ...
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Reset Register Definitions Reset Status Register The Reset Status (RSTSTAT) register is a read-only register which indicates the source of the most recent Reset event, a Stop Mode Recovery event, and a WDT timeout. Reading this register resets the upper ...
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WDT—Watchdog Timer Timeout Indicator If this bit is set WDT timeout occurs. A POR resets this pin. A Stop Mode Recovery from a change in an input pin also resets this bit. Reading this register resets this ...
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PS025011-1010 Z8 Encore Reset, Stop Mode Recovery, and Low-Voltage ® F1680 Series Product Specification 44 ...
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Low-Power Modes Overview The Z8 Encore! XP F1680 Series products have power-saving features. The highest level of power reduction is provided by the STOP mode. The next lower level of power reduction is provided by the HALT mode. Further ...
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To minimize current in STOP mode, all GPIO pins which are configured as digital inputs must be driven to one of the supply rails (V STOP mode using Stop Mode Recovery. For more details on Stop Mode Recovery, see Reset, ...
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Power Control Register Definitions Power Control Register 0 Each bit of the following registers disables a peripheral block, either by gating its system clock input or by removing power from the block. The default state of the low-power operational amplifier ...
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COMP0—Comparator 0 Disable Comparator 0 is Enabled (this applies even in STOP Mode) Comparator 0 is Disabled COMP1—Comparator 1 Disable Comparator 1 is Enabled (this applies even in STOP Mode) Comparator 1 ...
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General-Purpose Input/Output Overview The Z8 Encore! XP F1680 Series product supports a maximum of 37 port pins (Ports A–E) for general-purpose input/output (GPIO) operations. Each port contains control and data registers. The GPIO control registers determine data direction, open-drain, ...
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Architecture Figure 9 displays a simplified block diagram of a GPIO port pin and does not illustrate the ability to accommodate alternate functions and variable port current drive strength. Port Output Data Register DATA D Q Bus System Clock Figure ...
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Direct LED Drive The Port C pins provide a current synched output capable of driving an LED without requiring an external resistor. The output synchs current at programmable levels of 3 mA, 7 mA, 13 mA, and 20 mA. This ...
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External Clock Setup For systems using an external TTL drive, PB3 is the clock source for 20-pin, 28-pin, 40-pin, and 44-pin devices. In this case, configure PB3 for alternate function CLKIN. Write the Oscillator Control Register (see page 308) ...
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Table 15. Port Alternate Function Mapping (20-Pin Parts) (Continued) Port Pin Mnemonic PB0 Reserved Port B ANA0/AMPOUT PB1 Reserved ANA1/AMPINN PB2 Reserved ANA2/AMPINP PB3 CLKIN ANA3 PC0 Reserved Port C ANA4/C0INP/LED PC1 Reserved ANA5/C0INN/LED PC2 Reserved VREF/ANA6/LED PC3 COUT0 LED ...
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Table 16. Port Alternate Function Mapping (28-Pin Parts) Port Pin Mnemonic PA0 T0IN/T0OUT Port A Reserved PA1 T0OUT Reserved PA2 DE0 Reserved PA3 CTS0 Reserved PA4 RXD0/IRRX0 Reserved PA5 TXD0/IRTX0 Reserved PA6 T1IN/T1OUT SCL PA7 T1OUT SDA Note: Because there ...
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Table 16. Port Alternate Function Mapping (28-Pin Parts) (Continued) Port Pin Mnemonic PB0 Reserved Port B ANA0/AMPOUT PB1 Reserved ANA1/AMPINN PB2 Reserved ANA2/AMPINP PB3 CLKIN ANA3 PB4 Reserved ANA7 PB5 Reserved VREF Note: Because there are at most two choices ...
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Table 16. Port Alternate Function Mapping (28-Pin Parts) (Continued) Port Pin Mnemonic PC0 Reserved Port C ANA4/C0INP/ LED PC1 MISO ANA5/C0INN/ LED PC2 SS ANA6/LED PC3 COUT0 LED PC4 MOSI LED PC5 SCK LED PC6 T2IN/T2OUT LED PC7 T2OUT LED ...
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Table 17. Port Alternate Function Mapping (40-pin/44-pin Parts) Port Pin Mnemonic PA0 T0IN/T0OUT Port A Reserved PA1 T0OUT Reserved PA2 DE0 Reserved PA3 CTS0 Reserved PA4 RXD0/IRRX0 PA5 TXD0/IRTX0 PA6 T1IN/T1OUT Reserved PA7 T1OUT Reserved Note: Because there are at ...
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Table 17. Port Alternate Function Mapping (40-pin/44-pin Parts) (Continued) Port Pin Mnemonic PB0 Reserved Port B ANA0/AMPOUT PB1 Reserved ANA1/AMPINN PB2 Reserved ANA2/AMPINP PB3 CLKIN ANA3 PB4 Reserved ANA7 PB5 Reserved VREF Note: Because there are at most two choices ...
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Table 17. Port Alternate Function Mapping (40-pin/44-pin Parts) (Continued) Port Pin Mnemonic PC0 Reserved Port C ANA4/C0INP/LED ADC or Comparator 0 Input (P), or LED PC1 Reserved ANA5/C0INN/LED ADC or Comparator 0 Input (N), or LED PC2 SS ANA6/LED PC3 ...
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Table 17. Port Alternate Function Mapping (40-pin/44-pin Parts) (Continued) Port Pin Mnemonic PD0 RESET Port D Reserved PD1 C1INN Reserved PD2 C1INP Reserved PD3 CTS1/COUT1 Reserved PD4 RXD1/IRRX1 Reserved PD5 TXD1/IRTX1 Reserved PD6 DE1 Reserved PD7 COUT0 Reserved Note: Because ...
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Table 17. Port Alternate Function Mapping (40-pin/44-pin Parts) (Continued) Port Pin Mnemonic PE0 T4IN* Port E Reserved PE1 SCL Reserved PE2 SDA Reserved PE3 T4CHA* Reserved PE4 T4CHB* Reserved PE5 T4CHC* Reserved PE6 T4CHD* Reserved Note: Because there is only ...
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Table 18. GPIO Port Registers and Subregisters Port Register Mnemonic PxADDR PxCTL PxIN PxOUT Port Subregister Mnemonic Port Register Name PxDD PxAF PxOC PxHDE PxSMRE PxPUE PxAFS1 PxAFS2 Port A–E Address Registers The Port A–E address registers select the GPIO ...
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PADDR[7:0] Port Control Subregister Accessible using the Port A–E Control Registers 00H No function. Provides some protection against accidental port reconfiguration 01H Data Direction 02H Alternate Function 03H Output Control (Open-Drain) 04H High Drive Enable 05H Stop Mode Recovery Source ...
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Table 21. Port A–E Data Direction Subregisters (PxDD) BITS 7 6 DD7 DD6 FIELD 1 1 RESET R/W R/W R/W If 01H in Port A–E Address Register, accessible through the Port A–E Control Register ADDR DD[7:0]—Data Direction These bits control ...
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The alternate function selected through Alternate Function set subregisters are enabled. Port-pin operation is controlled by the alternate function. Port A–E Output Control Subregisters The Port A–E Output Control subregister Control register by writing Port A–E Output ...
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PHDE[7:0]—Port High Drive Enabled The Port pin is configured for standard output current drive. The Port pin is configured for high output current drive. Port A–E Stop Mode Recovery Source Enable Subregisters The Port A–E ...
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Table 26. Port A–E Pull-Up Enable Subregisters (PxPUE) BITS 7 6 PPUE7 PPUE6 FIELD 0 0 RESET R/W R/W R/W If 06H in Port A – E Address Register, accessible through the Port A ADDR PPUE[7:0]—Port Pull-up Enabled ...
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Alternate Functions selected by setting or clearing bits of this register is defined in Table 15 through Note: Alternate function selection on port pins must also be enabled as described in Port A–E Alternate Function Subregisters Table 28. Port ...
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Port A–E Output Data Register The Port A–E Output Data register Table 30. Port A–E Output Data Register (PxOUT) BITS 7 6 POUT7 POUT6 FIELD 0 0 RESET R/W R/W R/W ADDR POUT[7:0]—Port Output Data These bits contain the data ...
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Table 32 and Table 33 used to select one of four programmable current drive levels for each associated Port C[x] pin. Each Port C pin is individually programmable. Table 32. LED Drive Level High Bit Register (LEDLVLH) BITS 7 6 ...
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... For more information on interrupt servicing by the eZ8 CPU, refer to eZ8 CPU User Manual (UM0128). The eZ8 CPU User Manual is available on www.zilog.com. Interrupt Vector Listing on page 72 lists all the interrupts available in order of priority. The interrupt ...
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Table 34. Trap and Interrupt Vectors in Order of Priority Program Memory Priority * Vector Address Highest 0002H 0004H 003AH 003CH 0006H 0008H 000AH 000CH 000EH 0010H 0012H 0014H 0016H 0018H 001AH 001CH 001EH 0020H 0022H 0024H 0026H 0028H 002AH ...
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Architecture Figure 10 displays the interrupt controller block diagram. Port Interrupts Internal Interrupts Figure 10. Interrupt Controller Block Diagram Operation Master Interrupt Enable The master interrupt enable bit (IRQE) in the interrupt control register globally enables and disables interrupts. Interrupts ...
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Reset • Execution of a Trap instruction • Illegal Instruction Trap • Primary Oscillator Fail Trap • Watchdog Oscillator Fail Trap Interrupt Vectors and Priority The interrupt controller supports three levels of interrupt priority. Level 3 is the highest ...
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Software Interrupt Assertion Program code can generate interrupts directly. Writing 1 to the correct bit in the Interrupt Request register triggers an interrupt (assuming that interrupt is enabled). When the interrupt request is acknowledged by the eZ8 CPU, the bit ...
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T2I—Timer 2 Interrupt Request interrupt request is pending for Timer 2. interrupt request from Timer 2 is awaiting service. T1I—Timer 1 Interrupt Request interrupt request is pending for Timer 1. 1 ...
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PA7VI—Port A7 or LVD Interrupt Request interrupt request is pending for GPIO Port A7 or LVD. interrupt request from GPIO Port A7 or LVD. PA6CI—Port A6 or Comparator 0 Interrupt Request ...
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U1TXI—UART 1 Transmitter Interrupt Request interrupt request is pending for the UART 1 transmitter. interrupt request from the UART 1 transmitter is awaiting service. PCxI—Port C Pin x Interrupt Request interrupt ...
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Table 40. IRQ0 Enable Low Bit Register (IRQ0ENL) BITS 7 6 T2ENL T1ENL FIELD 0 0 RESET R R/W R/W ADDR T2ENL—Timer 2 Interrupt Request Enable Low Bit. T1ENL—Timer 1 Interrupt Request Enable Low Bit. T0ENL—Timer 0 Interrupt Request Enable ...
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PA7VENH—Port A Bit[7] or LVD Interrupt Request Enable High Bit. PA6C0ENH—Port A Bit[6] or Comparator 0 Interrupt Request Enable High Bit. PA5C1ENH—Port A Bit[5] or Comparator 1 Interrupt Request Enable High Bit. PADxENH—Port A or Port D Bit[x] (x=1, 2, ...
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Table 45. IRQ2 Enable High Bit Register (IRQ2ENH) BITS 7 6 Reserved MCTENH FIELD 0 0 RESET R/W R/W R/W ADDR Reserved—Must be 0. MCTENH—Multi-Channel Timer Interrupt Request Enable High Bit. U1RENH—UART1 Receive Interrupt Request Enable High Bit. U1TENH—UART1 Transmit ...
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Interrupt Edge Select Register The Interrupt Edge Select (IRQES) register is generated for the rising edge or falling edge on the selected GPIO Port A or Port D input pin. Table 47. Interrupt Edge Select Register (IRQES) BITS 7 ...
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PA5CS—PA5/Comparator 1 Selection PA5 is used for the interrupt for PA5CS interrupt request. The Comparator 1 is used for the interrupt for PA5CS interrupt request. PADxS—PAx/PDx Selection PAx is used for the interrupt for ...
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PS025011-1010 Z8 Encore ® F1680 Series Product Specification 84 Interrupt Controller ...
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Timers Overview The Z8 Encore! XP F1680 Series products contain three 16-bit reloadable timers that can be used for timing, event counting, or generation of pulse-width modulated signals. The timers’ features include: • 16-bit reload counter. • Programmable prescaler with ...
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Data Bus Block Control Peripheral Clock System Clock Timer Input Gate Input Capture Input Operation The timers are 16-bit up-counters. Minimum timeout delay is set by loading the value into the Timer Reload High and Low Byte registers, and setting ...
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When timer is operating on a peripheral clock, the timer clock is asynchronous Caution: to the CPU clock. To ensure error-free operation, disable the timer before modifying its operation (include changing the timer clock source). So any write to the ...
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Timer Operating Modes The timers can be configured to operate in the following modes. ONE-SHOT Mode In ONE-SHOT mode, the timer counts up to the 16-bit Reload value stored in the Timer Reload High and Low Byte registers. The Timer ...
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Triggered ONE-SHOT Mode In Triggered ONE-SHOT mode, the Timer operates as follows: 1. The Timer idles until a trigger is received. The Timer trigger is taken from the GPIO Port pin Timer Input alternate function. The TPOL bit in the ...
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Table 50. Triggered ONE-SHOT Mode Initialization Example (Continued) Register Value PAADDR 02H PACTL[1:0] 11B IRQ0ENH[5] 0B IRQ0ENL[5] 0B T0CTL1 83H Note: After receiving the input trigger, Timer 0 will 1. Count ABCDH timer clocks. 2. Upon Timer 0 reload, generate ...
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If desired, enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers using the Timer Output function, configure the associated GPIO port pin for the Timer Output alternate function. 8. ...
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Write to the Timer High and Low Byte registers to set the starting count value. This only affects the first pass in COUNTER mode. After the first timer Reload in COUNTER mode, counting always begins at the reset value ...
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Write to the Timer Control 2 register to choose the timer clock source. 3. Write to the Timer Control 0 register to set the timer interrupt configuration field TICONFIG. 4. Write to the Timer High and Low Byte registers ...
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Follow the steps below for configuring a timer for PWM Single Output mode and initiating the PWM operation: 1. Write to the Timer Control 1 register to: Disable the timer – Configure the timer for PWM mode – Set the ...
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PWM Dual Output Mode In PWM Dual Output mode, the timer outputs a Pulse Width Modulator output signal and also its complement through two GPIO Port pins. The Timer counts timer clocks up to the 16-bit Reload value. The timer ...
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Write to the Timer Control 0 register to set the timer interrupt configuration field TICONFIG. 6. Write to the Timer Reload High and Low Byte registers to set the Reload value (PWM period). The Reload value must be greater ...
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Follow the steps below for configuring a timer for CAPTURE mode and initiating the count: 1. Write to the Timer Control 1 register to: Disable the timer – Configure the timer for CAPTURE mode – Set the prescale value – ...
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If no Capture event occurs, the timer counts up to the 16-bit Compare value stored in the Timer Reload High and Low Byte registers. On reaching the Reload value, the timer gen- erates an interrupt, the count value in the ...
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COMPARE Mode In COMPARE mode, the timer counts up to the 16-bit maximum Compare value stored in the Timer Reload High and Low Byte registers. The Timer counts timer clocks up to 16-bit Reload value. On reaching the Compare ...
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GPIO input value and compare to the value stored in the TPOL bit. The timer counts up to the 16-bit Reload value stored in the Timer Reload High and Low Byte registers. The timer ...
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Timer High and Low Byte registers is reset to bit in Timer Control 0 register is set to indicate the timer interrupt is due to an input capture event Capture event occurs, the timer counts up to ...
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DEMODULATION Mode In DEMODULATION mode, the timer begins counting on the first external Timer Input transition. The desired transition (rising edge or falling edge or both) is set by the TPOL bit in the Timer Control 1 register and TPOLHI ...
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Clear the Timer TxPWM0 and TxPWM1 High and Low Byte registers required, enable the noise filter and set the noise filter control by writing to the relevant bits in the Noise Filter Control Register ...
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Table 51. DEMODULATION Mode Initialization Example (Continued) Register Value T0PWM1H 00H T0PWM1H 00H T0NFC C0H PAADDR 02H PACTL[1:0] 11B IRQ0ENH[5] 0B IRQ0ENL[5] 0B T0CTL1 84H Notes: After receiving the input trigger (rising or falling edge), Timer 0 will: 1. Start ...
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The Noise Filter has the following features: • Synchronizes the receive input data to the Timer Clock • NFEN (Noise Filter Enable) input selects whether the Noise Filter is bypassed (NFEN=0) or included (NFEN=1) in the receive data path NFCTL ...
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The Noise Filter delays the receive data by three Timer Clock cycles. The NEF output signal is checked when the filtered TxIN input signal is sampled. ...
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Timer Control Register Definitions Timer 0–2 High and Low Byte Registers The Timer 0–2 High and Low Byte (TxH and TxL) registers contain the current 16-bit timer count value. When the timer is enabled, a read from TxH causes the ...
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Timer Reload High and Low Byte Registers The Timer 0–2 Reload High and Low Byte (TxRH and TxRL) registers Table 55) store a 16-bit reload value, {TRH[7:0], TRL[7:0]}. Values written to the Timer Reload High Byte register are stored in ...
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Table 56. Timer 0–2 PWM0 High Byte Register (TxPWM0H) BITS 7 6 FIELD 0 0 RESET R/W R/W R/W ADDR Table 57. Timer 0–2 PWM0 Low Byte Register (TxPWM0L) BITS 7 6 FIELD 0 0 RESET R/W R/W R/W ADDR ...
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Table 59. Timer 0–2 PWM1 Low Byte Register (TxPWM1L) BITS 7 6 FIELD 0 0 RESET R/W R/W R/W ADDR PWM1H and PWM1L—Pulse Width Modulator 1 High and Low Bytes These two bytes, {PWM1H[7:0], PWM1L[7:0]}, store the 16-bit captured timer ...
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CSC—Cascade Timers Timer Input signal comes from the pin. For Timer 0, Input signal is connected to Timer 2 output. For Timer 1, Input signal is connected to Timer 0 output. For Timer 2, Input ...
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ONE-SHOT mode When the timer is disabled, the Timer Output signal is set to the value of this bit. When the timer is enabled, the Timer Output signal is complemented upon timer Reload. CONTINUOUS mode When the timer is disabled, ...
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PWM Dual Output mode Timer Output is forced Low (0) and Timer Output Complement is forced High (1) when the timer is disabled. When enabled, the Timer Output is forced High (1) upon PWM count match ...
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PRES—Prescale value The timer input clock is divided by 2PRES, where PRES can be set from The prescaler is reset each time the Timer is disabled. This insures proper clock division each time the Timer is ...
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PWM0UE—PWM0 Update Enable This bit determines whether writes to the PWM0 High and Low Byte registers are buffered when TEN = 1. Writes to these registers are not buffered when TEN = 0 regardless of the value of ...
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PWMxEO—PWM x Event Overrun This bit indicates that an overrun error has occurred. An overrun occurs when a new capture/compare event occurs before the previous PWMxEF bit is cleared. Clearing the associated PWMxEF bit in the TxSTAT register ...
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NFCTL—Noise Filter Control This field controls the delay and noise rejection characteristics of the Noise Filter. The wider the counter the more delay that is introduced by the filter and the wider the noise event that will be filtered. 000 ...
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PS025011-1010 Z8 Encore ® F1680 Series Product Specification 118 Timers ...
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Multi-Channel Timer Overview The Multi-Channel timer has a 16-bit up/down counter and a 4-channel Capture/Compare/ PWM channel array. This timer enables the support of multiple synchronous Capture/ Compare/PWM channels based on a single timer. The Multi-Channel Timer features include: • ...
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Timer Operation Multi-Channel Timer Counter The Multi-Channel Timer is based around a 16-bit up/down counter. The counter, depending on the TIMER mode counts up or down with each rising edge of the clock signal. Timer Counter Registers MCTH and ...
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Table 65. Timer Count Modes TMODE Timer Mode 00 Count Modulo 01 Reserved 10 Count Up/Down 11 Reserved Count Modulo Mode In the Count Modulo mode, the Timer counts up to the Reload Register value (max value = FFFFH ...
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Reload 0H Capture/Compare Channel Operation The Multi-Channel timer supports four Capture/Compare channels: CHA, CHB, CHC, and CHD. Each channel has the following features: • A 16-bit Capture/Compare Register (MCTCHyH and MCTCHyL registers) used to capture input event times or to ...
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Continuous Compare Operation In Continuous Compare operation, a channel interrupt is generated when the channel compare value matches the timer count. The channel event flag (CHyEF) is set in the Channel Status1 register (MCTCHS1) and the channel remains enabled. The ...
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Capture/Compare Channel Interrupt A channel interrupt is generated whenever there is a successful Capture/Compare Event on the Timer Channel and the associated CHIEN bit is set. Low-Power Modes Operation in HALT Mode When the eZ8 CPU is operating in HALT ...
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FFFFH Reload MCTCH0 MCTCH1 Figure 17. Count Up/Down Mode with PWM Channel Outputs and Deadband FFFFH Figure 18. Count Max Mode with Channel Compare PS025011-1010 Dead Time TCH0 Output TCH1 Output CI CI ...
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Multi-Channel Timer Control Register Definitions Multi-Channel Timer Address Map Table 66 defines the byte address offsets for the Multi-channel Timer registers. For saving address space, sub-address is used for Timer Control 0 register, Timer Control 1 register, Channel Status 0 ...
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Table 66. Multi-Channel Timer Address Map (Continued) Address/Sub-address Subregister Multi-Channel Timer High and Low Byte Registers The High and Low Byte (MCTH and MCTL) registers (see contain the current 16-bit MCT count value. ...
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When MCT is enabled, a read from MCTH causes the value in MCTL to be stored in a temporary holding register. A read from MCTL returns this temporary register when MCT is enabled. When MCT is disabled, reads from MCTL ...
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The value written to the MCTRH is stored in a temporary holding register. When a write to the MCTRL occurs, the temporary holding register value is written to the MCTRH. This operation allows simultaneous updates of the 16-bit MCT Reload ...
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Multi-Channel Timer Control 0, Control 1 Registers The Multi-Channel Timer Control registers (MCTCTL0, MCTCTL1) control Multi-Channel Timer operation. Writes to the PRES field of MCTCTL1 register are buffered when TEN = 1, and will not take effect until the ...
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The input frequency of the Timer Input Signal must not exceed one-fourth Note: the system clock frequency. Table 74. Multi-Channel Timer Control 1 Register (MCTCTL1) BITS 7 6 TEN Reserved FIELD 0 0 RESET R/W R R/W 00H in Sub-Address ...
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Multi-Channel Timer Channel Status 0 and Status 1 Registers Multi-Channel Timer Channel Status 0 and Status 1 Registers (MCTCHS0, MCTCHS1) indicate channel overrun and channel capture/compare event. Table 75. Multi-Channel Timer Channel Status 0 Register (MCTCHS0) BITS 7 6 Reserved ...
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Multi-Channel Timer Channel-y Control Registers Each channel has a control register to enable the channel, select the input/output polarity, enable channel interrupts and select the channel mode of operation. Table 77. Multi-Channel Timer Channel Control Register (MCTCHyCTL BITS 7 6 ...
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Capture Operation 0 = Count is captured on the rising edge of the Channel Input signal. Count is captured on the falling edge of the Channel Input signal. CHIEN—Channel Interrupt Enable This bit enables generation of channel interrupt. ...
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Table 79. Multi-Channel Timer Channel-y Low Byte Registers (MCTCHyL) BITS 7 6 FIELD 0 0 RESET R/W R/W R/W 02H, 03H, 04H, 05H in Sub-Address Register, accessible through SubRegister 1 ADDR D CHyH and CHyL—Multi-Channel ...
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PS025011-1010 Z8 Encore ® F1680 Series Product Specification 136 Multi-Channel Timer ...
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Watchdog Timer Watchdog Timer (WDT) helps protect against corrupted, or unreliable software and other system-level problems that may place the Z8 Encore! XP F1680 Series into unsuitable operating states. The WDT includes the following features: • On-chip RC oscillator • ...
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Watchdog Timer Refresh When first enabled, the WDT is loaded with the value in the WDT Reload registers. The WDT then counts down to Execution of the Reload value stored in the WDT Reload registers. Counting resumes following the reload ...
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WDT Reset in STOP Mode If enabled in STOP mode and configured to generate a Reset when a timeout occurs and the device is in STOP mode, the WDT initiates a Stop Mode Recovery. Both the WDT status bit ...
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Table 81. Watchdog Timer Reload High Byte Register (WDTH = FF2H) BITS 7 FIELD 0 RESET R/W R/W ADDR Table 82. Watchdog Timer Reload Low Byte Register (WDTL = FF3H) BITS 7 FIELD 0 RESET R/W R/W ADDR WDTH and ...
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LIN-UART The Local Interconnect Network Universal Asynchronous Receiver/Transmitter (LIN-UART full-duplex communication channel capable of handling asynchronous data transfers in standard UART applications and providing LIN protocol support. The LIN-UART is a superset of the standard Z8 Encore! ...
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Data Format for Standard UART Modes The LIN-UART always transmits and receives data in an 8-bit data format with the least significant bit first. An even-or-odd parity bit or multiprocessor address/data bit can be optionally added to the data stream. ...
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Figure 20. LIN-UART Asynchronous Data Format without Parity Figure 21. LIN-UART Asynchronous Data Format with Parity Transmitting Data Using Polled Method Follow the steps below to transmit data using the polled-operating method: 1. Write to the LIN-UART Baud Rate High ...
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Check the TDRE bit in the LIN-UART Status 0 register to determine if the Transmit Data Register is empty (indicated by a 1). If empty, continue to Data Register is full (indicated by a 0), continue to monitor the ...
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The LIN-UART is now configured for interrupt-driven data transmission. Because the LIN-UART Transmit Data Register is empty, an interrupt is generated immediately. When the LIN-UART Transmit interrupt is detected and there is transmit data ready to send, the associated interrupt ...
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Receiving Data Using the Interrupt-Driven Method The LIN-UART Receiver interrupt indicates the availability of new data (as well as error conditions). Follow the steps below to configure the LIN-UART receiver for interrupt-driven operation: 1. Write to the LIN-UART Baud ...
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Clear To Send Operation The Clear To Send (CTS) pin, if enabled by the Register performs flow control on the outgoing transmit data stream. The Clear To Send (CTS) input pin is sampled one system clock before any new character ...
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The Driver Enable to 1 Baud Rate (Hz) LIN-UART Special Modes The special modes of the LIN-UART are: • MULTIPROCESSOR Mode • LIN Mode The LIN-UART features a common control register (Control 0) that has a unique register address and ...
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MULTIPROCESSOR Mode Receive Interrupts When MULTIPROCESSOR (9-bit) mode is enabled, the LIN-UART processes only frames addressed to it. To determine whether a frame of data is addressed to the LIN-UART can be made in hardware, software or a combination ...
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LIN Protocol Mode The Local Interconnect Network (LIN) protocol as supported by the LIN-UART module is defined in rev 2.0 of the LIN Specification Package. The LIN protocol specification covers all aspects of transferring information between LIN Master and Slave ...
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LIN System Clock Requirements The LIN Master provides the timing reference for the LIN network and is required to have a clock source with a tolerance of ±0.5%. A slave with autobaud capability is required to have a baud clock ...
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The Synch character is transmitted by writing a must = 1 before writing). The Synch character is not transmitted by the hardware till the Break is complete. The Identifier character is transmitted by writing the appropriate value to the Transmit ...
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LIN Slave Operation LIN SLAVE mode is selected by setting [1:0] = LinState message by the Break which appears to the Slave as a break of at least 11 bit times in duration. The LIN-UART detects the Break and generates ...
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Transmit Shift Register has shifted out the first bit of a character. At this point, the Transmit Data Register may be written with the next character to send. This provides 7 bit periods of latency to load the ...
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LIN-UART Data- and Error-Handling Procedure displays the recommended procedure for use in LIN-UART receiver Figure 24 interrupt service routines. Figure 24. LIN-UART Receiver Interrupt Service Routine Flow PS025011-1010 Z8 Encore ...
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Baud Rate Generator Interrupts If the bit of the Multiprocessor Control Register (LIN-UART Control 1 Register BRGCTL with MSEL = 000b LIN-UART Receiver interrupt asserts when the LIN-UART Baud Rate Generator reloads. This action allows the Baud Rate Generator to ...
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Noise Filter A noise filter circuit is included which filters noise on a digital input signal (such as UART Receive Data) before the data is sampled by the block. This is likely requirement for protocols with a ...
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A 2-bit counter is shown for convenience, the operation of wider counters is 11b similar. The output of the filter switches from when the counter counts down from to ; and switches from 0 to ...
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LIN-UART Control Register Definitions The LIN-UART control registers support the LIN-UART, the associated Infrared Encoder/Decoder, and the noise filter. For more information on the infrared operation, see Infrared Encoder/Decoder LIN-UART Transmit Data Register Data bytes written to the LIN-UART ...
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LIN-UART Status 0 Register The LIN-UART Status 0 Register identifies the current LIN-UART operating configuration and status. mode. Table 86 on page 161 describes the Status 0 Register for LIN mode. A more detailed discussion of each bit follows each ...
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Receive Data Available (RDA)—This bit indicates that the LIN-UART Receive Data Register has received data. Reading the LIN-UART Receive Data Register clears this bit. Parity Error (PE)—This bit indicates that a parity error has occurred. Reading the Receive Data Register ...
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FE — Framing Error framing error occurred. framing error occurred. BRKD Break Detect — LIN break occurred. LIN break occurred. TDRE — Transmitter Data Register Empty ...
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LIN Slave Autobaud Complete (ATB)—This bit is set in LIN SLAVE mode when an autobaud character is received. If the ABIEN bit is set in the LIN Control Register, then a receive interrupt is generated when this bit is set. ...
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Table 88. Mode Status Fields MULTIPROCESSOR NEWFRM Mode Status Field Status bit denoting the start of a new frame. Reading the LIN-UART Receive Data Register resets this bit The current byte is not the first data ...
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LIN-UART Control 0 Register The LIN-UART Control 0 Register UART’s transmit and receive operations. A more detailed discussion of each bit follows the table. Table 89. LIN-UART Control 0 Register (U0CTL0 = F42H) BITS 7 TEN FIELD 0 RESET R/W ...
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Receive Enable (REN)—This bit enables or disables the receiver. Clear To Send Enable (CTSE)—See the bit descriptions in Parity Enable (PEN)—This bit enables or disables parity. Even or odd is determined by the PSEL bit. Parity Select (PSEL)—See the bit ...
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Bit Position Value Description [7,5] MULTIPROCESSOR Mode MPMD[1:0] 00 The LIN-UART generates an interrupt request on all data and address bytes. 01 The LIN-UART generates an interrupt request only on received address bytes. 10 The LIN-UART generates an interrupt request ...
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MPMD [1:0]—MULTIPROCESSOR Mode The LIN-UART generates an interrupt request on all received bytes (data and address). The LIN-UART generates an interrupt request on all received address bytes. The LIN-UART generates an interrupt request ...
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Noise Filter Control Register When MSEL = 001b provides control for the digital noise filter. Table 91. Noise Filter Control Register (U0CTL1 = F43H with MSEL = 001b) BITS FIELD RESET CPU ACCESS ADDR Note Read; R/W = ...
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LIN Control Register When = MSEL 010b operation. A more detailed discussion of each bit follows the table. Table 92. LIN Control Register (U0CTL1 = F43H with MSEL = 010b) BITS FIELD RESET CPU ACCESS ADDR Note: R/W = Read/Write ...
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Bit Position [1:0] TxBreakLength LIN MASTER Mode (LMST)—See the bit descriptions in LIN SLAVE Mode (LSLV)—See the bit descriptions in Autobaud Enable (ABEN)—See the bit descriptions in Autobaud Interrupt Enable (ABIEN)—See the bit descriptions in 170. LIN State Machine (LinState[1:0])—The ...
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Bit Position [7:0] COMP_ADDR LIN-UART Baud Rate High and Low Byte Registers The LIN-UART Baud Rate High and Low Byte registers (see combine to create a 16-bit baud rate divisor value (BRG[15:0]) that sets the data transmission rate (baud rate) ...
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The UART must be disabled when updating the Baud Rate registers because the high and Note: low registers must be written independently. The LIN-UART data rate is calculated using the following equation for standard UART operation: UART Data ...
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Table 96. LIN-UART Baud Rates, 20.0 MHz System Clock BRG Applicable Divisor Actual Rate Rate (kHz) (Decimal) (kHz) 1250.0 1 1250.0 625.0 2 625.0 250.0 5 250.0 115.2 11 113.64 57.6 22 56.82 38.4 33 37.88 19.2 65 19.23 Table ...
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Table 99. LIN-UART Baud Rates, 3.579545 MHz System Clock BRG Applicable Divisor Actual Rate Rate (kHz) (Decimal) (kHz) 1250.0 N/A N/A 625.0 N/A N/A 250.0 1 223.72 115.2 2 111.9 57.6 4 55.9 38.4 6 37.3 19.2 12 18.6 Table ...
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PS025011-1010 Z8 Encore ® F1680 Series Product Specification 176 LIN-UART ...
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Infrared Encoder/Decoder Overview The Z8 Encore! XP F1680 Series products contain a fully-functional, high-performance UART to Infrared Encoder/Decoder (Endec). The Infrared Endec is integrated with an on-chip UART to allow easy communication between the Z8 Encore! and IrDA Physical ...
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Infrared Endec through the RXD pin, decoded by the Infrared Endec and passed to the UART. Communication is half-duplex, that is, simultaneous data transmission and reception is not allowed. The baud rate is set by ...
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Receiving IrDA Data Data received from the infrared transceiver using the is decoded by the Infrared Endec and passed to the UART. The UART’s baud rate clock is used by the Infrared Endec to generate the demodulated signal ( UART. ...
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The window remains open until the count again reaches 8 (in other words, 24 baud clock periods since the previous pulse is detected), giving the Endec a sampling window of minus 4 baud rate clocks to plus 8 baud rate ...
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Analog-to-Digital Converter The Z8 Encore! includes an eight-channel Successive Approximation Register Analog-to- Digital converter (SAR ADC). The ADC converts an analog input signal to a 10-bit binary number. The features of the ADC include: • Eight analog input sources multiplexed ...
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Internal Voltage Reference Generator Analog-to-Digital Converter Reference Input 10 Data Output Analog Input BUSY ADCLK ADCEN START Figure 30. Analog-to-Digital Converter Block Diagram ADC Timing Each ADC measurement consists of 3 phases: 1. Input sampling (programmable, minimum of 1.8 µs). ...
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START SAMPLE/HOLD BUSY ADC Clock BUSY Reference Buffer The reference buffer, RBUF, supplies the reference voltage for the ADC. When enabled, the internal voltage reference generator supplies the ADC and this voltage is available on the ...
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Internal Voltage Reference Generator The Internal Voltage Reference Generator provides the voltage, VR2, for the RBUF. VR2 is 1.6 V. Calibration and Compensation You can calibrate and store the values into Flash, or the user code can perform a ...
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Bit Position Value (H) [3:0] ANAIN 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1100 1101 Others ADC Raw Data High Byte Register The ADC Raw Data High Byte Register (see bits of raw data from the ...
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ADC Data High Byte Register The ADC Data High Byte Register output. Access to the ADC Data High Byte Register is Read-only. Reading the ADC Data High Byte Register latches data in the ADC Low Bits Register. Table 103. ADC ...