Z8F16800144ZCOG Zilog, Z8F16800144ZCOG Datasheet - Page 244

• Manufacturer Part Number: Z8F16800144ZCOG
• Description: KIT DEV FOR Z8F642 MCU 44 PIN
• Manufacturer: Zilog
• Series: Z8 Encore!®r
• Type: MCUr

Specifications of Z8F16800144ZCOG

• Contents: Hardware, Software and Documentation
• For Use With/related Products: Z8F642
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4678

PS025011-1010
S
Slave Address
Slave Transaction Diagrams
In the following transaction diagrams, the shaded regions indicate data transferred from
the Master to the Slave, and the unshaded regions indicate the data transferred from the
Slave to the Master. The transaction field labels are defined as follows:
Slave Receive Transaction with 7-Bit Address
The data transfer format for writing data from a Master to a Slave in 7-bit address mode 
is displayed in
Controller operating as a slave in 7-bit addressing mode and receiving data from the bus
master.
Figure 47. Data Transfer Format—Slave Receive Transaction with 7-Bit Address
1. The software configures the controller for operation as a slave in 7-bit addressing
2. The bus master initiates a transfer, sending the address byte. In SLAVE mode, the 
3. The software responds to the interrupt by reading the I2CISTAT Register (which
S
W
A
A
P
mode, as follows:
(a) Initialize the
(b) Optionally set the
(c) Initialize the
(d) Set
I
the master to the slave). The I
accept the transaction. The
interrupt. The
the slave. The I
load the first data byte.
clears the
Because
2
C controller recognizes its own address and detects that R/W bit = 0 (written from
or MASTER/SLAVE mode with 7-bit addressing.
Start
Write
Acknowledge
Not Acknowledge
Stop
IEN
RD
SAM
Figure
W=0
= 0, no immediate action is required until the first byte of data is received.
= 1 in the I
RD
bit). After seeing the
2
C controller holds the SCL signal Low waiting for the software to
MODE
SLA[6:0]
bit in the I2CISTAT Register is cleared to 0, indicating a Write to 
47. The procedure that follows describes the I
A
GCE
field in the I
2
P R E L I M I N A R Y
C Control Register. Set
bit.
SAM
bits in the I
Data
2
C controller acknowledges indicating it is available to
bit in the I2CISTAT Register is set to 1, causing an
2
SAM
C Mode Register for either SLAVE ONLY mode
A
2
bit to 1, the software checks the
C Slave Address Register.
Data
NAK
Z8 Encore! XP
= 0 in the I
A
Product Specification
I2C Master/Slave Controller
Data
2
2
C Master/Slave 
C Control Register.
®
A/A
F1680 Series
RD
bit.
P/S
230