Z8F16800144ZCOG Zilog, Z8F16800144ZCOG Datasheet - Page 241

• Manufacturer Part Number: Z8F16800144ZCOG
• Description: KIT DEV FOR Z8F642 MCU 44 PIN
• Manufacturer: Zilog
• Series: Z8 Encore!®r
• Type: MCUr

Specifications of Z8F16800144ZCOG

• Contents: Hardware, Software and Documentation
• For Use With/related Products: Z8F642
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4678

PS025011-1010
The first 7 bits transmitted in the first byte are
most-significant bits of the 10-bit address. The lowest bit of the first byte transferred is the
write control bit.
The data transfer procedure for a Read operation to a 10-bit addressed slave is as follows:
1. The software initializes the
2. The software writes
3. The software asserts the
4. The I
5. The I
6. After the first bit has been shifted out, a transmit interrupt is asserted.
7. The software responds by writing the least significant eight bits of address to 
8. The I
9. The I
10. The I
11. The I
12. The software responds by setting the
13. The software writes
14. If the user chooses to read only one byte, the software responds by setting the 
MASTER/SLAVE mode with 7- or 10-bit addressing (the I
mixing of slave address types). The
when addressed as a slave (but not for the remote slave). The software asserts the IEN
bit in the I
0 (write) to the I
Register.
the I
high period of SCL.
If the slave does not acknowledge the address byte, the I
bit in the I
Register. The software responds to the Not Acknowledge interrupt by setting the
bit and clearing the
sends the
transaction is complete, and the following steps can be ignored.
Register (the lower byte of the 10-bit address).
the I
generate a repeated
to the I
NAK
2
2
bit of the I
2
2
2
2
2
2
C Data Register.
C controller generates a transmit interrupt.
C controller sends a
C controller loads the I
C controller completes shifting of the first address byte.
C slave sends an Acknowledge by pulling the SDA signal Low during the next
C controller loads the I
C controller shifts out the next eight bits of the address. After the first bit shifts,
2
C Data Register.
STOP
2
2
C Control Register.
C Status Register, sets the
2
condition on the bus and clears the
C Control Register.
2
C Data Register.
TXI
START
11110b
11110b
P R E L I M I N A R Y
bit. The I
START
START
condition.
MODE
, followed by the two most-significant address bits and a
, followed by the 2-bit slave address and a 1 (Read)
2
2
C Shift Register with the contents of the I
C Shift Register with the contents of the I
bit of the I
2
field in the I
condition.
C controller flushes the Transmit Data Register,
MODE
START
ACKV
field selects the address width for this mode
11110XX
2
C Control Register.
bit and clears the
bit of the I
2
C Mode Register for 
STOP
Z8 Encore! XP
. The two
2
C Control Register to 
2
C controller sets the NCKI
and
2
C bus protocol allows the
Product Specification
I2C Master/Slave Controller
ACK
NCKI
XX
bits are the two
bit in the I
bits. The
®
F1680 Series
2
2
C Data
C Data
2
C State
STOP
227