Z8F16800144ZCOG Zilog, Z8F16800144ZCOG Datasheet - Page 126

• Manufacturer Part Number: Z8F16800144ZCOG
• Description: KIT DEV FOR Z8F642 MCU 44 PIN
• Manufacturer: Zilog
• Series: Z8 Encore!®r
• Type: MCUr

Specifications of Z8F16800144ZCOG

• Contents: Hardware, Software and Documentation
• For Use With/related Products: Z8F642
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4678

PS025011-1010
ONE-SHOT mode
When the timer is disabled, the Timer Output signal is set to the value of this bit.
When the timer is enabled, the Timer Output signal is complemented upon timer
Reload.
CONTINUOUS mode
When the timer is disabled, the Timer Output signal is set to the value of this bit.
When the timer is enabled, the Timer Output signal is complemented upon timer
Reload.
COUNTER mode
When the timer is disabled, the Timer Output signal is set to the value of this bit.
When the timer is enabled, the Timer Output signal is complemented upon timer
Reload. 
0 = Count occurs on the rising edge of the Timer Input signal.
1 = Count occurs on the falling edge of the Timer Input signal.
PWM Single Output mode
0 = Timer Output is forced Low (0) when the timer is disabled. When enabled, 
1 = Timer Output is forced High (1) when the timer is disabled. When enabled, 
CAPTURE mode
0 = Count is captured on the rising edge of the Timer Input signal.
1 = Count is captured on the falling edge of the Timer Input signal.
COMPARE mode
When the timer is disabled, the Timer Output signal is set to the value of this bit.
When the timer is enabled, the Timer Output signal is complemented on timer Reload.
GATED mode
0 = Timer counts when the Timer Input signal is High (1) and interrupts are 
1 = Timer counts when the Timer Input signal is Low (0) and interrupts are 
CAPTURE/COMPARE mode
0 = Counting is started on the first rising edge of the Timer Input signal. The 
1 = Counting is started on the first falling edge of the Timer Input signal. The 
generated on the rising edge of the Timer Input.
current count is captured on subsequent falling edges of the Timer Input signal.
the Timer Output is forced High (1) on PWM count match and forced 
Low (0) on Reload.
the Timer Output is forced Low (0) on PWM count match and forced
generated on the falling edge of the Timer Input. 
current count is captured on subsequent rising edges of the Timer Input signal.
High (1) on Reload.
P R E L I M I N A R Y
Z8 Encore! XP
Product Specification
®
F1680 Series
Timers
112