Z8F16800144ZCOG Zilog, Z8F16800144ZCOG Datasheet - Page 218

• Manufacturer Part Number: Z8F16800144ZCOG
• Description: KIT DEV FOR Z8F642 MCU 44 PIN
• Manufacturer: Zilog
• Series: Z8 Encore!®r
• Type: MCUr

Specifications of Z8F16800144ZCOG

• Contents: Hardware, Software and Documentation
• For Use With/related Products: Z8F642
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4678

®
Z8 Encore! XP
F1680 Series
Product Specification
204
functions as a Watchdog Timer monitoring the SCK signal. The BRG counter is 
reloaded every time a transition on SCK occurs while SS is asserted. The Baud Rate
Reload registers must be programmed with a value longer than the expected time 
between the SS assertion and the first SCK edge, between SCK transitions while SS is
asserted, and between the last SCK edge and SS deassertion. A timeout indicates the
Master is stalled or disabled. Writing a 1 to ABT clears this error flag.
ESPI Interrupts
ESPI has a single interrupt output which is asserted when any of the TDRE, TUND, COL,
ABT, ROVR or RDRNE bits are set in the ESPI Status register. The interrupt is a pulse
which is generated when any one of the source bits initially sets. The TDRE and RDRNE
interrupts may be enabled/disabled via the Data Interrupt Request Enable (DIRQE) bit of
the ESPI Control register.
A transmit interrupt is asserted by the TDRE status bit when the ESPI block is 
enabled and the DIRQE bit is set. The TDRE bit in the Status register is cleared 
automatically when the Data register is written or the ESPI block is disabled. Once the
Data register is loaded into the shift register to start a new transfer, the TDRE bit will be
set again, causing a new transmit interrupt. In SLAVE mode, if information is being
received but not transmitted the transmit interrupts may be eliminated by selecting
Receive Only mode (ESPIEN1,0 = 01). A Master cannot operate in Receive Only mode
since a write to the ESPI (Transmit) Data register is still required to initiate the 
transfer of a character even if information is being received but not transmitted 
by the software application.
A receive interrupt is generated by the RDRNE status bit when the ESPI block is 
enabled, the DIRQE bit is set and a character transfer completes. At the end of the
character transfer, the contents of the shift register are transferred into the data register,
causing the RDRNE bit to assert. The RDRNE bit is cleared when the Data Buffer is read
as empty. If information is being transmitted but not received by the software 
application, the receive interrupt can be eliminated by selecting Transmit Only mode
(ESPIEN1,0 = 10) in either MASTER or SLAVE modes. When information is being sent
and received under interrupt control, RDRNE and TDRE will both assert simultaneously
at the end of a character transfer. Since the new receive data is in the Data register, 
the receive interrupt must be serviced before the transmit interrupt.
ESPI error interrupts occur if any of the TUND, COL, ABT, and ROVR bits in
the ESPI Status register are set. These bits are cleared by writing a 1. If the ESPI is
disabled (ESPIEN1, 0 = 00), an ESPI interrupt can be generated by a 
Baud Rate Generator timeout. This timer function must be enabled by setting the
BRGCTL bit in the ESPICTL register. This timer interrupt does not set any of the 
bits of the ESPI Status register.
PS025011-1010
P R E L I M I N A R Y
Enhanced Serial Peripheral Interface