Z8F16800144ZCOG Zilog, Z8F16800144ZCOG Datasheet - Page 247

• Manufacturer Part Number: Z8F16800144ZCOG
• Description: KIT DEV FOR Z8F642 MCU 44 PIN
• Manufacturer: Zilog
• Series: Z8 Encore!®r
• Type: MCUr

Specifications of Z8F16800144ZCOG

• Contents: Hardware, Software and Documentation
• For Use With/related Products: Z8F642
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4678

PS025011-1010
1. The software configures the controller for operation as a slave in 7-bit addressing
2. The Master initiates a transfer by sending the address byte. The SLAVE mode 
3. The software responds to the interrupt by reading the I2CISTAT Register, thereby
4. SCL is released and the first data byte is shifted out.
5. After the first bit of the first data byte has been transferred, the I
6. The software responds to the transmit data interrupt (
7. After the data byte has been received by the master, the master transmits an
8. The bus cycles through
9. The software responds to the Not Acknowledge interrupt by clearing the
10. When the Master has completed the final acknowledge cycle, it asserts a
11. The Slave I
mode, as follows:
(a) Initialize the
(b) Optionally set the
(c) Initialize the
(d) Set
I
master from the slave). The I
to accept the transaction. The
causing an interrupt. The
clearing the
data byte into the I2CDATA Register. The software sets the
Register to enable transmit interrupts. When the master initiates the data transfer, 
the I
the I2CDATA Register.
TDRE
data byte into the I2CDATA Register, which clears
Acknowledge instruction (or Not Acknowledge instruction if this byte is the final data
byte).
If the software has not yet loaded the next data byte when the master brings SCL Low
to transfer the most significant data bit, the slave I
the data register has been written. When a Not Acknowledge instruction is received by
the slave, the I
Not Acknowledge interrupt to be generated.
in the I2CCTL Register and by asserting the
empty the data register.
RESTART
I2CISTAT Register).
2
C controller finds an address match and detects that the R/W bit = 1 (read by the
or MASTER/SLAVE mode with 7-bit addressing.
2
C controller holds SCL Low until the software has written the first data byte to
bit, which asserts the transmit data interrupt.
IEN
condition on the bus.
2
SAM
C controller asserts the
= 1 in the I
2
C controller sets the
bit. Because
MODE
SLA[6:0]
GCE
field in the I
2
P R E L I M I N A R Y
Step 5
C Control Register. Set
RD
bit.
bits in the I
2
bit is set to 1, indicating a Read from the slave.
C controller acknowledges, indicating that it is ready 
SAM
RD
to
= 1, the software responds by loading the first 
Step 7
bit in the I2CISTAT Register is set to 1, 
2
STOP/RESTART
NCKI
C Mode Register for either SLAVE ONLY mode
2
until the final byte has been transferred. 
C Slave Address Register.
bit in the I2CISTAT Register causing the
FLUSH
NAK
2
C controller holds SCL Low until
TDRE
Z8 Encore! XP
bit of the I2CCTL Register to
= 0 in the I
TDRE
interrupt (set
.
= 1) by loading the next
TXI
Product Specification
I2C Master/Slave Controller
2
2
bit in the I2CCTL
C Control Register.
C controller sets the
SPRS
®
F1680 Series
bit in
TXI
STOP
bit 
or
233