Z8F16800144ZCOG Zilog, Z8F16800144ZCOG Datasheet - Page 88

• Manufacturer Part Number: Z8F16800144ZCOG
• Description: KIT DEV FOR Z8F642 MCU 44 PIN
• Manufacturer: Zilog
• Series: Z8 Encore!®r
• Type: MCUr

Specifications of Z8F16800144ZCOG

• Contents: Hardware, Software and Documentation
• For Use With/related Products: Z8F642
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4678

PS025011-1010
Caution:
Caution:
Interrupt Vectors and Priority
Interrupt Assertion
Good coding style that avoids lost interrupt requests:
The interrupt controller supports three levels of interrupt priority. Level 3 is the highest
priority, Level 2 is the second highest priority, and Level 1 is the lowest priority. If all the
interrupts are enabled with identical interrupt priority (for example, all as Level 2
interrupts), the interrupt priority is assigned from highest to lowest as specified in
on page 72. Level 3 interrupts are always assigned higher priority than Level 2 interrupts
which, in turn, always are assigned higher priority than Level 1 interrupts. Within each
interrupt priority level (Level 1, Level 2, or Level 3), priority is assigned as specified in
Table 34
Trap, Watchdog Timer Oscillator Fail Trap, and Illegal Instruction Trap always have
highest (Level 3) priority.
Interrupt sources assert their interrupt requests for only a single-system clock period
(single pulse). When the interrupt request is acknowledged by the eZ8 CPU, the
corresponding bit in the Interrupt Request register is cleared until the next interrupt
occurs. Writing 0 to the corresponding bit in the Interrupt Request register likewise clears
the interrupt request.
Poor coding style that can result in lost interrupt requests:
•
•
•
•
•
The following coding style that clears bits in the Interrupt Request registers
is not recommended. All incoming interrupts received between execution of
the first LDX command and the final LDX command are lost.
To avoid missing interrupts, use the following coding style to clear bits in the Interrupt
Request 0 register:
Reset
Execution of a Trap instruction
Illegal Instruction Trap
Primary Oscillator Fail Trap
Watchdog Oscillator Fail Trap
on page 72. Reset, Watchdog Timer interrupt (if enabled), Primary Oscillator Fail
LDX r0, IRQ0
AND r0, MASK
LDX IRQ0, r0
ANDX IRQ0, MASK
P R E L I M I N A R Y
Z8 Encore! XP
Product Specification
®
Interrupt Controller
F1680 Series


Table 34
74