Z8F16800144ZCOG Zilog, Z8F16800144ZCOG Datasheet - Page 148

• Manufacturer Part Number: Z8F16800144ZCOG
• Description: KIT DEV FOR Z8F642 MCU 44 PIN
• Manufacturer: Zilog
• Series: Z8 Encore!®r
• Type: MCUr

Specifications of Z8F16800144ZCOG

• Contents: Hardware, Software and Documentation
• For Use With/related Products: Z8F642
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4678

Table 78. Multi-Channel Timer Channel-y High Byte Registers (MCTCHyH)
PS025011-1010
BITS
FIELD
RESET
R/W
ADDR
Capture Operation
Multi-Channel Timer Channel-y High and Low Byte Registers
R/W
7
0
0 = Count is captured on the rising edge of the Channel Input signal.
1 = Count is captured on the falling edge of the Channel Input signal.
CHIEN—Channel Interrupt Enable
This bit enables generation of channel interrupt. A channel interrupt is generated when-
ever there is a capture/compare event on the Timer Channel.
0 = Channel interrupt is disabled.
1 = Channel interrupt is enabled.
CHUE—Channel Update Enable
This bit determines whether writes to the Channel High and Low Byte registers are
buffered when TEN = 1. Writes to these registers are not buffered when TEN = 0
regardless of the value of this bit.
0 = Writes to the Channel High and Low Byte registers are buffered when TEN = 1 
1 = Writes to the Channel High and Low Byte registers are not buffered when TEN = 1.
CHOP—Channel Operation method
This field determines the operating mode of the channel. For a detailed description of the
operating modes, see
000 = One-Shot Compare operation.
001 = Continuous Compare operation.
010 = PWM Output operation.
011 = Capture operation.
100 – 111 = Reserved.
Each channel has a 16-bit capture/compare register defined here as the 
Channel-y High and Low Byte registers. When the timer is enabled, writes to these 
registers are buffered and loading of the registers is delayed till the next timer end count,
unless CHUE = 1.
02H, 03H, 04H, 05H in Sub-Address Register, accessible through SubRegister 0
and only take affect on the next end of cycle count.
R/W
6
0
Count Up/Down Mode
R/W
5
0
P R E L I M I N A R Y
R/W
4
0
CHyH
on page 121. 
R/W
3
0
Z8 Encore! XP
R/W
2
0
Product Specification
R/W
Multi-Channel Timer
1
0
®
F1680 Series
R/W
0
0
134