Z8F16800144ZCOG Zilog, Z8F16800144ZCOG Datasheet - Page 234

• Manufacturer Part Number: Z8F16800144ZCOG
• Description: KIT DEV FOR Z8F642 MCU 44 PIN
• Manufacturer: Zilog
• Series: Z8 Encore!®r
• Type: MCUr

Specifications of Z8F16800144ZCOG

• Contents: Hardware, Software and Documentation
• For Use With/related Products: Z8F642
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4678

PS025011-1010
Start and Stop Conditions
Software Control of I
generator (BRG) counts down to 1. The baud rate generator reloads and continues
counting, providing a periodic interrupt. None of the bits in the I2CISTAT Register 
are set, allowing the BRG in the I
timer when the I
The Master generates the START and STOP conditions to start or end a transaction. 
To start a transaction, the I
signal Low while SCL is High. To complete a transaction, the I
STOP
signal is High. These START and STOP events occur when the
the I
transfer currently under way including the Acknowledge phase finishes before the
or
The I
MODE[1:0]
for MASTER/SLAVE or SLAVE ONLY mode and configures the slave for 7-bit or 10-bit
addressing recognition.
MASTER/SLAVE mode can be used for:
•
•
•
In SLAVE ONLY mode, the START bit of the I
cannot initiate a master transaction by accident), and operation to SLAVE ONLY mode is
restricted thereby preventing accidental operation in MASTER mode. The software 
controls I
or by polling the I
To use interrupts, the I
by executing an EI instruction. The
enable transmit interrupts. An I
Register to determine the cause of the interrupt.
To control transactions by polling, the
interrupt bits in the I
of the state of the
STOP
MASTER ONLY operation in a Single Master/One or More Slave I
MASTER/SLAVE in a Multimaster/multislave I
SLAVE ONLY operation in an I
2
2
C Control Register are written by software to begin or end a transaction. Any byte
condition by creating a Low-to-High transition of the SDA signal while the SCL
C controller is configured via the I
condition occurs.
2
C transactions by enabling the I
field of the I
2
C controller is disabled.
TXI
2
C Status Register.
2
C Status Register should be polled. The
2
bit.
C interrupt must be enabled in the interrupt controller and followed
2
C Transactions
2
C Mode Register allows the configuration of the I
2
C controller generates a
P R E L I M I N A R Y
2
C interrupt service routine then checks the I
2
C controller to be used as a general-purpose 
TXI
2
C system.
TDRE
bit in the I
2
2
C Control and I
C controller interrupt in the interrupt controller
,
RDRF
2
C Control Register is ignored (software
,
2
SAM
START
C Control Register must be set to
2
C system.
Z8 Encore! XP
,
ARBLST
2
C Mode registers. The
condition by pulling the SDA
TDRE
2
START
C controller generates a
Product Specification
I2C Master/Slave Controller
,
SPRS
bit asserts regardless
and
, and
2
®
C system.
F1680 Series
STOP
2
2
C Status
C controller
NCKI
bits in
START
220