Z8F16800144ZCOG Zilog, Z8F16800144ZCOG Datasheet - Page 175
Z8F16800144ZCOG
Manufacturer Part Number
Z8F16800144ZCOG
Description
KIT DEV FOR Z8F642 MCU 44 PIN
Manufacturer
Zilog
Series
Z8 Encore!®r
Type
MCUr
Specifications of Z8F16800144ZCOG
Contents
Hardware, Software and Documentation
For Use With/related Products
Z8F642
For Use With
269-4661 - KIT ACC ETHERNET SMART CABLE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-4678
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PS025011-1010
Receive Data Available (RDA)—This bit indicates that the LIN-UART Receive Data
Register has received data. Reading the LIN-UART Receive Data Register clears this bit.
Parity Error (PE)—This bit indicates that a parity error has occurred. Reading the
Receive Data Register clears this bit.
Overrun Error (OE)—This bit indicates that an overrun error has occurred. An overrun
occurs when new data is received and the Receive Data Register is not read. Reading the
Receive Data Register clears this bit.
Framing Error (FE)—This bit indicates that a framing error (no STOP bit following data
reception) was detected. Reading the Receive Data Register clears this bit.
Break Detect (BRKD)—This bit indicates that a break occurred. If the data bits, parity/
multiprocessor bit, and STOP bit(s) are all zeros then this bit is set to 1. Reading the
Receive Data Register clears this bit.
Transmitter Data Register Empty (TDRE)—This bit indicates that the Transmit Data
Register is empty and ready for additional data. Writing to the Transmit Data Register
resets this bit.
Transmitter Empty (TXE)—This bit indicates that the Transmit Shift Register is empty
and character transmission is finished.
Clear To Send Signal (CTS)—When this bit is read it returns the level of the CTS
signal. If LBEN = 1, the CTS input signal is replaced by the internal Receive Data
Available signal to provide flow control in loopback mode. CTS only affects transmission
if the CTSE bit = 1.
Table 86. LIN-UART Status 0 Register—LIN Mode (U0STAT0 = F41H)
RDA
0 = The Receive Data Register is empty.
1 = There is a byte in the Receive Data Register.
PLE
0 = Transmit and Receive data match.
1 = Transmit and Receive data do not match.
OE
0 = No autobaud or data overrun error occurred.
1 = An autobaud or data overrun error occurred.
BITS
FIELD
RESET
R/W
ADDR
Note: R = Read
—
—
—
Receive Data and Autobaud Overrun Error
Physical Layer Error
Receive Data Available
RDA
R
7
0
PLE
R
6
0
P R E L I M I N A R Y
OE
R
5
0
FE
F41H, F49H
R
4
0
BRKD
R
3
0
Z8 Encore! XP
TDRE
R
2
1
Product Specification
®
TXE
R
1
1
F1680 Series
LIN-UART
ATB
R
0
0
161
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